Abstract: An integrated circuit including a DRAM is disclosed, wherein the DRAM includes a memory array including a plurality of pass gate transistors and a plurality of memory elements. The pass gate transistors include a gate material selected to provide a substantially near mid-gap work function or greater. The DRAM also includes a peripheral area including a plurality of logic transistors. In a preferred embodiment the pass gate transistors are silicon-on-insulator transistors.
Abstract: A low drop-out regulator is configured to provide high output current with a fast response during transient conditions, while also maintaining low quiescent current under DC conditions. An exemplary low drop-out regulator has an error amplifier, a current feedback amplifier, and a pass device. The low drop-out regulator includes a composite amplifier feedback configuration, with the current feedback amplifier being decoupled from the overall composite feedback configuration and configured to provide effective compensation. As a result, the current feedback amplifier can be configured to operate with low current supplied from the error amplifier and to drive the control terminal of the pass device with sufficiently high current as demanded by a load device. In addition, the current feedback amplifier can be configured to permit the voltage at the control terminal of the pass device to operate from rail-to-rail.
Abstract: A composite loop compensation circuit and method for a low drop-out regulator configured to facilitate stable operation at very low output load currents is provided. An exemplary low drop-out regulator includes an error amplifier, a pass device, and a composite loop compensation circuit. The compensation loop compensation circuit includes a plurality of segmented sense devices, a plurality of switches and a biasing component. The plurality of segmented sense devices are configured to sense an output load current, i.e., the current from the output terminal of the pass device. The plurality of switches are coupled between the plurality of segmented sense devices and a biasing component. Composite loop compensation circuit is configured to adjust the dominant first pole of the composite feedback loop based on the output load current through biasing of the active resistor component.
Type:
Grant
Filed:
July 8, 2002
Date of Patent:
March 9, 2004
Assignee:
Texas Instruments Incorporated
Inventors:
Hubert J. Biagi, Haoran Zhang, Thomas L. Botker
Abstract: A voltage supply circuit in which parasitic oscillation of a charge pump driver circuit can be restrained, charge pump driving currents can be generated at a stable oscillation frequency, and a desired boosting voltage can be supplied to a load circuit.
Abstract: A clock distribution system and method for an integrated circuit includes a power supply line and a plurality of clock distribution elements. The power supply line is operable to provide resistive-capacitive (RC) filtered power. The clock distribution elements are coupled to the power supply line. The clock distribution elements are operable to be powered by the RC filtered power supply to distribute a reference clock signal.
Abstract: A low-cost, high-performance, reliable micromirror package (300) that replaces the ceramic substrate in conventional packages with a printed circuit board substrate (30) and a molded plastic case (33), and the cover glass with a window (36), preferably an optically clear plastic window. The printed circuit board substrate (30) allows for either external bond pads or flex cable connection of the micromirror package to the projector's motherboard. These packages support flexible snap-in, screw-in, ultrasonic plastic welding, or adhesive welding processes to overcome the high cost seam welding process of many conventional packages.
Abstract: A differential amplifier includes an input stage (13) and an output stage (100) including an output transistor (M11) having a source coupled to a supply voltage (VDD), a gate coupled to a terminal (14) of the input stage, and a drain coupled to an output conductor (22). A recovery circuit (1A) is coupled between the supply voltage and the gate of the output transistor for limiting the voltage on the gate of the output transistor in response to the output voltage be within a predetermined range of the supply voltage and includes a recovery transistor (M4) with a source coupled to the output conductor and a drain coupled to the gate of the output transistor and a common-gate amplifier (29A) having a built-in offset a first input coupled to the output conductor, a second input coupled to the supply voltage, and an output coupled to the gate of the recovery transistor.
Type:
Grant
Filed:
June 5, 2002
Date of Patent:
March 9, 2004
Assignee:
Texas Instruments Incorporated
Inventors:
Vadim V. Ivanov, Shilong Zhang, Gregory H. Johnson
Abstract: A comparator-type sense amplifier compares a constant voltage that was read out of a FeRAM cell to a sequence of reference voltage levels. A multiple-comparison operation includes (a) reading out data to a bit line, (b) applying a first/next reference voltage, (c) comparing the bit line voltage to the applied reference voltage, and (d) repeating steps (b) and (c) one or more times. The multiple comparison operation can be used to characterize operation of an FeRAM cell, predict or detect an FeRAM cell that may introduce a bit error, or to read a multi-bit value from an FeRAM cell.
Type:
Grant
Filed:
April 2, 2002
Date of Patent:
March 9, 2004
Assignees:
Agilent Technologies, Inc., Texas Instruments, Inc.
Inventors:
Juergen T. Rickes, Hugh P. McAdams, James W. Grace
Abstract: A digital system is provided with a memory (42) that can be shared by two or more data requestors (10, 20). Two modes of access are provided. In a shared access memory (SAM) access mode, all of the data requestors can sequentially access the memory. In a host only memory (HOM) access mode, the memory is connected directly to one of the requestors, such as a host processor (10), so that high bandwidth transfers can be performed. The HOM access mode is entered when a priority assigned to the host processor is set to be higher than a priority assigned to any other requester. Registers for holding the priority assignments can be written by at least one of the requesters.
Type:
Grant
Filed:
June 9, 2000
Date of Patent:
March 9, 2004
Assignee:
Texas Instruments Incorporated
Inventors:
Laurent Six, Armelle Laine, Daniel Mazzocco, Gerald Ollivier
Abstract: A function graphing method for detecting discontinuities. The method involves scanning piecewise linear segments of the function graph and detecting large changes in the angle between segments. When such changes in angle are found, a bisection routine is performed to determine whether a discontinuity exists between the end points of a segment.
Abstract: A branch metric computation using limited bits by clipping the dynamic range and/or approximating the square of the difference between a sample value and the target value by a lookup table or piecewise linear with comparable slopes.
Type:
Grant
Filed:
February 18, 2000
Date of Patent:
March 9, 2004
Assignee:
Texas Instruments Incorporated
Inventors:
Michael Ming Tak Leung, Leo Ki Chun Fu, Borivoje Nikolic, James Kar Shing Chiu
Abstract: An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path generally operable for emulation control.
Type:
Grant
Filed:
November 1, 1999
Date of Patent:
March 9, 2004
Assignee:
Texas Instruments Incorporated
Inventors:
Gary L. Swoboda, Martin D. Daniels, Joseph A. Coomes
Abstract: The comparator input stage uses low voltage transistors 20 and 21 as the input pair. They have a small threshold voltage, and hence support a low common mode. The circuit includes a current sink 22 coupled to the input pair 20 and 21; a first resistor 33 coupled between a first branch of the input pair and a voltage node V24; a second resistor 36 coupled between a second branch of the input pair and the voltage node V24; a first transistor 23 coupled to the voltage node V24; a second transistor 24 having a gate coupled to a gate of the third transistor 23; a third resistor 32 coupled to a first end of the second transistor 24; and a current source 29 coupled to a second end of the second transistor 24 for controlling a voltage across the third resistor 32 wherein the voltage across the third resistor 32 sets a voltage at the voltage node V24. This voltage at the voltage node V24 serves as an open loop regulation for protection of the input pair transistors 20 and 21.
Type:
Grant
Filed:
December 9, 2002
Date of Patent:
March 9, 2004
Assignee:
Texas Instruments Incorporated
Inventors:
Sujoy Chakravarty, Pentakota A. Visvesvaraya
Abstract: Apparatus and methods are presented to allow the creation of a personalized audio signal for a communication device., An option to record audio input and create a call signal audio file is selected via an input mechanism (203). Audio input is recorded when a record button (204) is pressed and the recording is terminated when the record button (204) is pressed a second time. Processing circuitry (220) optionally applies audio compression, filtering and encoding algorithms to said audio input and creates a call signal audio file. The call signal audio file is then stored in the memory circuitry designated for call signal audio files (210). Additional audio output circuitry (207) plays the call signal audio file when an incoming call is detected by the transceiver (201).
Abstract: A micromirror (110) includes a frame portion (112), a gimbal portion (114) and a mirror portion (116) formed from a single piece of material. A plurality of truss members (140/142) are disposed beneath the gimbal portion (114) and mirror portion (116), allowing the gimbal and mirror portions (114/116) to be made of a thinner material, reducing the mass and increasing the resonant frequency of the micromirror device (110).
Abstract: A system (10) and method (30) for precisely depositing a solder compound onto a substrate (18). The system (10) generally includes a receiving member (20) having a rotatable portion (21) adapted to receive a planar substrate (18), a horizontal member (12) for depositing solder balls (11) on the substrate (18), and a contact member (14), located between the receiving member (20) and horizontal member (12). The contact member comprises an aligner plate (14) having a pair of stoppers (15) protruding therefrom. Advantageously, pivotable portion (21) of the system (10) establishes the planarity of the substrate (18), with respect to the horizontal mount (12) allowing for the solder balls (11) to be mounted thereon, preventing the substrate (18) from being slightly misaligned, warped, and/or tilted.
Abstract: The specification discloses a method and related system for naming files in which digital images are kept in digital camera equipment. More particularly, the specification discloses that file names for images and video captured by digital camera equipment are assigned by the user by speaking the file name into a microphone of the digital camera. A digital signal processor within the camera reads the spoken file name, and using voice recognition software, converts the spoken word or words into corresponding word or words within the system. The captured image or images are then saved using the file name assigned by the user.
Abstract: A method and system for measuring the temporal response of a micromirror array to a variety of driving signals. A micromirror array is illuminated with a coherent light source so that a diffraction pattern is reflected from the micromirror array. One or more photodetectors are aligned with spots of light in the diffraction pattern that correspond to orders of the diffraction pattern. Diffraction pattern theory predicts that the intensity of these spots of light will vary as the tilt angle of the micromirrors is changed. Thus, by measuring the relative intensity of the spots of light as the micromirror array is provided with a variety of driving signals, many performance characteristics of the micromirror array can be measured. Some of these characteristics include the impulse response, the forced resonant frequency (i.e. the natural frequency), the damped resonant frequency, the quality factor of the micromirror response, the damping factor of the micromirror response, and the frequency transfer function.
Type:
Application
Filed:
August 29, 2002
Publication date:
March 4, 2004
Applicant:
Texas Instruments Incorporated
Inventors:
David Joseph Mehrl, Kun Cindy Pan, Mark Henry Strumpell, Rand Derek Carr
Abstract: A DMT modem (40) is disclosed, in which a combined time domain equalizer and per-tone equalizer is applied to a received DMT signal. The combined equalizer includes a first FFT function (44) that is applied to a set of samples in a time-domain signal after the application of a time domain equalizer (42). The first FFT function (44) produces an initial FFT result, that is accumulated with a sliding FFT (46) performed upon difference values in the time domain samples. The sliding FFT results are applied to a per-ton equalizer (48) which applies a set of complex coefficients determined in training of the modem. A simple 1-tap FEQ (50) then can recover the signal. The combined equalizer enables per-tone equalization, in a manner that is compatible with conventional DSL training standards. According to a second embodiment, the per-tone equalization is performed only on selected tones of the multitone signal.
Abstract: A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.