Patents Assigned to Texas Instruments
  • Publication number: 20040036145
    Abstract: A method of manufacturing a bipolar junction transistor results in an integrated polysilicon base contact and field plate element minimally spaced from a polysilicon emitter contact by using a single mask to define respective openings for these elements. In particular, a dielectric layer is deposited on a semiconductor wafer and has two openings defined by a single masking step, one opening above an emitter region and a second opening above a base-collector junction region. Polysilicon is deposited on the dielectric layer and selectively doped in the areas of the openings. Thus for an NPN transistor for example, the area above the emitter opening is doped N type and the area above the base/field plate opening is doped P type. The doped polysilicon is patterned and etched to leave a polysilicon emitter contact and an integrated polysilicon base contact and field plate within the respective openings.
    Type: Application
    Filed: August 23, 2002
    Publication date: February 26, 2004
    Applicant: Texas Instruments Incorporated
    Inventor: Sheldon Douglas Haynie
  • Patent number: 6696896
    Abstract: A pole and zero circuit for changing the position of a pole, or a zero, of an amplifier including a capacitor to change the position of the pole or zero for the amplifier, a first current path for the capacitor, a variable impedance device in the first current path to connect the capacitor to the amplifier, and a current source to control the impedance of the variable impedance device.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: February 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Jeremy Kuehlwein, Craig M. Brannon
  • Patent number: 6696861
    Abstract: A switch mode controller circuit includes: a hysteretic comparator HYST_COMP for monitoring an output of a switch mode circuit; a standard comparator PHASE_COMP for monitoring a phase of the switch mode circuit; a logic block having a first input coupled to a clock signal generator Oscillator, a second input coupled to an output of the hysteretic comparator HYST_COMP, and a third input coupled to an output of the standard comparator PHASE_COMP, wherein the logic block generates switching cycles based on a fixed ON/OFF time during a first part of a cycle and based on a hysteretic control during a second part of the cycle.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: February 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: David J. Baldwin, Zbigniew J. Lata, Sanmukh M. Patel, Ross E. Teggatz
  • Patent number: 6697916
    Abstract: A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory circuit (506(n). Validity circuitry (VI) is connected to the memory circuit and is operable to indicate if each segment of the plurality of segments holds valid data. Block transfer circuitry (700, 702) is connected to the memory circuit and is operable to transfer a block of data (1650) to a selected portion of segments (1606) of the cache memory circuit. Fetch circuitry associated with the memory cache is operable to transfer data from a pre-selected region of the secondary memory (1650) to a particular segment of the plurality of segments and to assert a first valid bit corresponding to the segment when the miss detection circuitry (1610) detects a miss in the segment. Direct memory access (DMA) circuitry (1610) is connected to the memory cache for transferring data between the memory cache and a selectable region (1650) of a secondary memory.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: February 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Serge Lasserre, Gerard Chauvel
  • Patent number: 6697084
    Abstract: A tone display method which prevents degradation in image quality of moving images when the subfield method is utilized without an increase in cost. When tone display is performed with 256 tones with respect to one certain color, in each frame, segments 1 to 6 in time are set corresponding to the plural time-shared time bands of the color and each segment includes one or several subfields (sf). In each case, as the tone is increased by 42 (or 43) for segments 1 through 6, sequentially, the subfields in the segment being lit so that the tone is increased continuously.
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: February 24, 2004
    Assignees: Texas Instruments Incorporated, Matsushita Electric Industrial Co. Ltd.
    Inventors: Hideki Ohmae, Hisakazu Hitomi, Adam J. Kunzman
  • Patent number: 6696332
    Abstract: Methods are disclosed for forming gate dielectrics for MOSFET transistors, wherein a bilayer deposition of a nitride layer and an oxide layer are used to form a gate dielectric stack. The nitride layer is formed on the substrate to prevent oxidation of the substrate material during deposition of the oxide layer, thereby avoiding or mitigating formation of low-k interfacial layer.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: February 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Mark Robert Visokay, Antonio Luis Pacheco Rotondaro, Luigi Colombo
  • Patent number: 6697416
    Abstract: A digital spread spectrum clock generator. The generator includes a digital waveform generator adapted to generate a sequence of digital words representing a predetermined varying waveform, and an accumulator. The accumulator includes a first two input adder and a second two input adder, the second adder having its output stored and applied to a first input of the second adder. The first two input adder is adapted to receive at a first input a control word, to receive at a second input the sequence of digital words, and to provide a sum output which is provided to a second input of the second adder. One of the bits of the output of the second adder is usable as a spread spectrum clock, or it may be provided to a phase locked loop to reduce jitter.
    Type: Grant
    Filed: September 12, 2000
    Date of Patent: February 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Richard E. Jennings
  • Patent number: 6697642
    Abstract: Apparatus for a wireless communication network, comprises: a directional beam antenna, an antenna controller for directing said directional beam antenna in an optimum signal quality beam direction, and coding means operable at two or more coding rates, to switch between said rates responsive to said controller changing said antenna beam direction.
    Type: Grant
    Filed: July 19, 2000
    Date of Patent: February 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: David R. Thomas
  • Patent number: 6697982
    Abstract: A method for enabling test vectors to be generated for a customer designed integrated circuit having an embedded vendor circuit is disclosed. The embedded vendor circuit has a proprietary circuit and a nonproprietary circuit. At least one pseudo input is defined to represent a portion of the nonproprietary circuit to emulate the nonproprietary circuit output. An output node of the embedded vendor circuit to which an input of the customer designed circuit is connectable is identified. A test netlist is created which represents circuitry that produces output states at the output node which would be generated by the embedded vendor circuit thereat. The test netlist includes at least one pseudo input and the output node, without including a full netlist of either the proprietary or nonproprietary circuits, and can be used to generate scan test vectors for the customer designed integrated circuit by the automatic test vector generating software program.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: February 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Srinivasa Chakravarthy, Rubin A. Parekhji, Julio C. Hernandez, Kenneth M. Butler
  • Patent number: 6696998
    Abstract: An apparatus for generating a digital signal representative of an analog signal includes two signal conversion devices, each having an analog signal section coupled with an input locus and a digital signal section coupled between the analog signal section and an output locus. The signal conversion devices receive sampled analog signals that are phase-offset by a first phase difference. Two feedback devices are each coupled between the output locus of one signal conversion device and the analog signal section of the other signal conversion device to convey feedback signals that are phase-offset by a second phase difference. The first phase difference and the second phase difference cooperate to affect power density spectrum of a resultant digital output signal at at least one predetermined frequency. The resultant digital output signal is a summing of a digital output signals presented by the two signal conversion devices at their output loci.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: February 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Feng Ying, Franco Maloberti
  • Patent number: 6697184
    Abstract: An optical system 200 includes a light source 202, such as a laser diode. A rotatable mirror 208 is positioned to receive a light beam 220 from the light source 202. A collimating lens 218 is positioned to receive a reflected light beam 222 from the rotatable mirror 208. The collimating lens 218 preferably has a focal length that is about equal to the sum of the distance between the light source 202 and the mirror 208 and the mirror 208 and the lens 218.
    Type: Grant
    Filed: January 29, 2002
    Date of Patent: February 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Robert C. Keller, Luisa Angelica Zepeda
  • Patent number: 6697492
    Abstract: A technique for realizing high-speed and high-precision acoustic reproduction using acoustic speakers. The audio signal processing system has a sub-band analysis filter bank that divides the entire frequency band of an input audio signal into multiple sub-bands. Filter coefficient calculation circuits identify equalizable sub-bands and compares equalizable sub-bands and corresponding sub-bands from output audio signals in order to calculate filter coefficients. A sub-band convolution filter bank and a filter circuit perform frequency convolution on calculated filter coefficients for equalizable sub-bands and process input audio signals on the basis of this convolution.
    Type: Grant
    Filed: April 27, 1999
    Date of Patent: February 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Hirohisa Yamaguchi, Yoshito Higa
  • Patent number: 6697003
    Abstract: Dynamic element matching systems and methods are provided in which a current dynamic element matching code is generated according to a previous dynamic element matching code, a digital input code, and a dither code. The current dynamic element matching code is then used along with the digital input code to select digital to analog converter elements.
    Type: Grant
    Filed: April 17, 2003
    Date of Patent: February 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Feng Chen
  • Patent number: 6696824
    Abstract: A variable DC/DC converter system is provided that includes a feedback voltage device and a compensation device. The compensation device and compensation components are integrated into a single integrated circuit. The feedback voltage device is integrated into the single integrated circuit. The values of a first resistor and a second resistor determine the output voltage of the DC/DC converter system. The first resistor and second resistor can be external to the integrated circuit and selectable to provide a desired output voltage. Alternatively, the first resistor can be integrated into the integrated circuit, while the second resistor is external to the integrated circuit and selectable to provide a desired output voltage.
    Type: Grant
    Filed: September 5, 2002
    Date of Patent: February 24, 2004
    Assignee: Texas Instruments Incorported
    Inventors: Alan Michael Johnson, Thomas L. Fowler
  • Patent number: 6696644
    Abstract: A plastic package for use in semiconductor devices, which has a plurality of metallic terminals exposed on a package surface and a metallic bump attached to each of said terminals. The bumps are made of reflowable metal and have approximately uniform height. An adherent layer of polymer material covers the package surface and surrounds each of the bumps to form a solid meniscus. The layer has a thickness between a quarter and one half of the bump height. An analogous methodology applies to plastic assembly boards.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: February 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Tz-Cheng Chiu, Manjula N. Variyam
  • Patent number: 6697108
    Abstract: A MOS architecture for reading rows of pixels in an area array imager. After initial setup, individual pixels are read one row at a time using one clock pulse per pixel.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: February 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Zhiliang Julian Chen, Eugene G. Dierschke
  • Patent number: 6696757
    Abstract: A metallurgical interconnection for electronic devices is described, wherein the interconnection has first and second interconnection metals. The first metal is shaped to enlarge the contact area, thus providing maximum mechanical interconnection strength, and to stop nascent cracks, which propagate in the interconnection. Preferred shapes include castellation and corrugation. The castellation may include metal protrusions, which create wall-like obstacles in the interconnection zones of highest thermomechanical stress, whereby propagating cracks are stopped. The surface of the first metal has an affinity to form metallurgical contacts. The second metal is capable of reflowing. The first metal is preferably copper, and the second metal tin or a tin alloy.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: February 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Mohammad Yunus, Anthony L. Coyle
  • Patent number: 6696337
    Abstract: In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: February 24, 2004
    Assignees: Hitachi, Ltd., Texas Instruments Inc.
    Inventors: Isamu Asano, Robert Tsu
  • Publication number: 20040032911
    Abstract: An ADSL transceiver hybrid circuit uses one or more isolated couplers (optical couplers, capacitors, or the like) configured to minimize the transmit signal component in the receive signal path by providing an isolated transmit signal feedback, thereby providing echo cancellation, isolating the telephone loop from the analog front end, and eliminating the need for a complex high-pass filter. The ADSL transceiver provides isolation and echo cancellation by: (a) generating a signal within the analog loop (e.g., telephone loop, or “local loop”) corresponding to a differential transmit signal; (b) receiving a composite signal from the analog loop corresponding to the sum of the transmit signal generated on the analog loop and the receive signal; (c) producing an isolated transmit signal (e.g.
    Type: Application
    Filed: August 16, 2002
    Publication date: February 19, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Zhonghua Wu, C.R. Teeple
  • Publication number: 20040034828
    Abstract: A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit (38) is disclosed. The LDPC code is arranged as a macro matrix (H) whose rows and columns represent block columns and block rows of a corresponding parity check matrix (Hpc). Each non-zero entry corresponds to a permutation matrix, such as a cyclically shifted identity matrix, with the shift corresponding to the position of the permutation matrix entry in the macro matrix. The block columns of the macro matrix are grouped, so that only one column in the macro matrix group contributes to the parity check sum in any given row. The decoder circuitry includes a parity check value estimate memory (52) which may be arranged in banks (252a-d) that can be logically connected in various data widths and depths. A parallel adder (54) generates extrinsic estimates that are applied to parity check update circuitry (56) for generating new parity check value estimates.
    Type: Application
    Filed: December 26, 2002
    Publication date: February 19, 2004
    Applicant: Texas Instruments Incorporated
    Inventor: Dale E. Hocevar