Abstract: The output slew rate of a differential transmission line driver (13) can be limited by suitably controlling signal slew rates (52) at the control inputs (neg, pos) of the drive switches (M1-M4) that control current flow through the load impedance (Rload) of the driver.

Abstract: The invention describes a method for forming integrated circuit interconnects. A capping layer (50) is formed on a low k dielectric layer (40). The capping layer (50) and the low k dielectric layer (40) are etched to form a via and/or trench in the low k dielectric (4) which is filled with a conducting material (90) (95).

Abstract: The purpose of this invention is to ensure an active use of the inverse short-channel effect in the ratio circuit and to guarantee stable operation at low power source voltage. In this ratio circuit, N-channel MOS transistor 12 of CMOS circuit 10 on one side forms the drive element, while P-channel MOS transistor 18 of CMOS circuit 16 on the other side forms the load element. Said N-channel MOS transistor 12 on the drive side and P-channel MOS transistor 16 on the load side have their drain terminals electrically connected to each other through transfer gate 22 made of N-channel MOS transistor. MOS transistor 12 on the drive side has a single channel CHa with the inverse short-channel effect. MOS transistor 18 on the load side has plural, e.g., two, channels CHb1 and CHb2, connected in tandem, each of which displays the inverse short-channel effect.

Abstract: A CMOS bus driver circuit includes an output stage of two complementary MOS transistors and an input stage, where in the connection of the source-drain paths of the MOS transistors (P1, N1) of the input stage a diode (D) is inserted so that the flow of a current in the direction of the MOS transistor (P1) connected to the supply voltage terminal (14) of the input stage is blocked, its cathode being connected to the gate of the one MOS transistor (P2) of the output stage. Connected in parallel to the diode D is the source-drain path of a further MOS transistor (P4), the gate of which is connected to the circuit output (18).

Abstract: A method and apparatus are disclosed for achieving a desired thickness profile in a semiconductor device (44) using a flow-flange reactor (10), by adjusting input flow ratios in the flow-flange (12) of the reactor (10). A target thickness profile is established. A first set of optimum input flow ratios are then determined in response to the target thickness profile, based upon a first plurality of sample thickness profiles and a first plurality of sets of sample input flow ratios, wherein each of the sample thickness profiles corresponds to one of the first plurality of sets of sample input flow ratios. The input flow ratios of the reactor (10) are then adjusted in response to the first optimum set of input flow ratios.

Abstract: A folding circuit is provided for outputting a periodic function representative of an analog input signal. The circuit includes at least two preamplifiers and a third differential amplifier circuit coupled to the preamplifier circuits for providing a bias current such that the flow of current is regulated through one of the preamplifier circuits at any given time, thereby providing a periodic function representative of an analog input signal.

Abstract: The present invention is a code preparation system (12) which accepts input code (11) in intermediate code format, our source code format which is first translated into intermediate format, analyzes the intermediate code, then provides optimization information, hints, and/or directions (collectively referred to as “optimization information”) for optimizing execution of the intermediate code by a code interpretive runtime environment, such as a Java Virtual Machine. The code interpretive runtime environment is operable to selectively implement the optimization information received from the code preparation system (12). The optimization information is provided to the code interpretive runtime environment in the form of additional attributes added to a class file (14) generated by the code preparation system (12).

Abstract: An R-2R type DA converter where the resistance value of the weighting resistors is set to a value calculated by adding the resistance value error to twice the standard resistance value. The resistance value of the terminating resistor (third-value resistor) is set to a value wherein the resistance value error is subtracted from twice the standard resistance value. With these resistance values, when a digital data signal is incremented even if the output voltage immediately before the digital signal is incremented is larger than the output voltage immediately after the digital signal is incremented, the output voltage immediately after the digital signal is incremented will not be excessively large compared to the output voltage immediately after the digital signal is incremented.

Abstract: A text-to-pronunciation system (11) includes a large training set of word pronunciations (19) and an extractor for extracting language specific information from the training set to produce pronunciations for words not in its training set. A learner (13) forms pronunciation guesses for words in the training set and for finding a transformation rule that improves the guesses. A rule applier (15) applies the transformation rule found to guesses. The learner (13) repeats the finding of another rule and the rule applier (15) applies the new rule to find the rules that improves the guesses the most.

Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.

Abstract: A memory traffic access controller (18) responsive to a plurality of requests to access a memory. The controller includes circuitry (18d) for associating, for each of the plurality of requests, an initial priority value corresponding to the request. The controller further includes circuitry (18b, 18d, 18e, 18f) for changing the initial priority value for selected ones of the plurality of requests to a different priority value. Lastly, the controller includes circuitry for outputting (18d) a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value.

Abstract: The invention relates to an improved substrate (100) using a layer (112) or region (130) of porous silicon that is created in the bulk silicon substrate material (110) to increase the resistivity of the substrate (100) thus making it suitable for passive component integration directly on the motherboard (200) or chip (230) and useful for high frequency applications due to its low loss, low dielectric properties. One or more passive components such as inductors (214), resistors (212) and capacitors (216) can be integrated on the device (140) over the porous silicon region (130). The high resistivity of the device makes it ideal for integration on a single platform using conventional wafer fab processes since loss at radio frequencies is comparably less when compared to a pure silicon substrate.

Abstract: A sequential color display system using three spatial light modulators and dichroic filters to sequentially provide a primary color light beam to a projection spatial light modulator. A set of dichroic filters separates a white light beam into primary colored light beams. Each primary colored light beam is modulated by a spatial light modulator to selectively allow it to travel to a second set of dichroic filters. The second set of dichroic filters recombines the primary color light beams—only one of which is typically active at any given time—to form a sequential color light beam. A projection spatial light modulator selectively modulates the sequential color light beam to form a sequential color image projected onto an image plane.

Abstract: An apparatus for filtering an input signal includes a first second order filter section having an output and an intermediate output, a second second order filter section having an input connected to the output of the first second order filter, and a gain stage coupling the output of the first second order filter section and the intermediate output of the first second order filter section to the output of the second second order filter section. The gain stage is coupled such that a transfer function between the output of the second second order filter section and the input of the second second order filter section is a biquadratic transfer function.

Abstract: A semiconductor memory device (300) having a parallel test circuit is disclosed. A test data path receives parallel I/O line (I/O0-I/O7) values, and generates therefrom test result data values (PASS and DATA_TST). The test result data values (PASS and DATA_TST) are coupled to a two-bit register (312) and output in a sequential fashion to an open drain output driver (314). In this manner, test result data values are provided by driving an output (DQ) in a rapid sequential fashion, rather than placing the output at one of three states (such as logic high state, a logic low state, or a high impedance state).

Abstract: The instant invention describes a programmable neuron MOSFET structure formed on SOI substrates. A number of input capacitor structures (241, 231) are formed on a SOI substrate. The substrate region of the capacitors (330, 340) are completely isolated from each other by isolation structures (270). In addition the transistor structure (210) of the neuron MOSFET is completely isolated from the capacitor structures (241, 231) by the isolation structure (270). The neuron MOSFET also comprises a contiguous floating conductive layer (200, 230, and 240) which forms the gate structure of the capacitors (230, 240) and the floating gate (200) of the transistor structure.

Abstract: A capacitor electrode and method of making having increased surface area because of the presence of pits in the side walls of the electrode thus increasing the capacitance of the capacitor while still maintaining the packing density of the integrated circuit.

Abstract: An integrated circuit package (50) may include an integrated circuit chip (22) having an integrated circuit (14). A lead frame (28) may be opposite the integrated circuit chip (22). The lead frame (28) may include at least one lead (30) electrically coupled to the integrated circuit (14) by a connector (42). The lead (30) may be within a periphery (32) of the integrated circuit chip (22). An encapsulant (44) may cover the integrated circuit (14), the connector (42) and a portion of the lead frame (28). A remaining portion of the lead frame (28) may be exposed from the encapsulant (44).

Abstract: An integrated circuit can have plural core circuits, each having a test access ports that is defined in IEEE Standar 1149.1. Access to and control of these ports is though a test linking moduled. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emudulation.

Abstract: This invention is a data processing system including a central processing unit executing program instructions to manipulate data, at least one level one cache, a level two unified cache, a directly addressable memory and a direct memory access unit adapted for connection to an external memory. A superscalar memory transfer controller schedules plural non-interfering memory movements to and from the level two unified cache and the directly addressable memory each memory cycle in accordance with a predetermined priority of operation. The level one cache preferably includes a level one instruction cache and a level one data cache. The superscalar memory transfer controller is capable of scheduling plural cache tag memory read accesses and one cache tag memory write access in a single memory cycle. The superscalar memory transfer controller is capable of scheduling plural of cache access state machines in a single memory cycle.