Abstract: A communications system with a circuit having a plurality of communications ports capable of multispeed operation and operable in a first mode that includes address resolution and in a second mode that excludes address resolution and includes a first memory, a plurality of protocol handlers, a bus connected to the protocol handlers, a second memory connected to the bus and a memory controller connected to the bus and the second memory for selectively comparing addresses, transferring data between the protocol handlers and the second memory, and transferring data between the second memory and the first memory. A first embodiment is a local area network controller having a first circuit with a plurality of communications ports capable of multispeed operation and operable in a first mode that includes address resolution and in a second mode that excludes address resolution, and an address lookup circuit interconnected with the first circuit.

Abstract: A system and method for matching a device to a transmission line are disclosed. A matching circuit having optically coupled devices is biased so that harmonics of a reference signal, such as a dial tone, are eliminated. Suppression of the reference signal harmonics indicates a correct impedance match between the matching circuit and the transmission line. The matching circuit also provides two-wire to four-wire conversion. After the matching circuit's impedance is adjusted, the circuit gain is balanced and the circuit is further biased to eliminate echoes. The impedance matching and circuit biasing operations are controlled by a digital signal processor. Before data or other signals are processed by the digital signal processor, an inverse transfer function is derived for the matching circuit. Received signals are convolved with the inverse transfer function to compensate for matching circuit distortion.

Abstract: A high-speed differential offset comparator circuit, providing a comparator function at a predetermined offset voltage. The differential offset comparator circuit includes a substantially zero offset comparator circuit having a first and a second differential input. The differential offset comparator circuit also includes a first pre-amplifier circuit and a second pre-amplifier circuit having an output coupled to the first and the second differential input, respectively, of the substantially zero offset comparator circuit. The pre-amplifier circuits are capable of providing a controllable offset to the differential offset comparator circuit. Each pre-amplifier circuit includes a first MOS transistor and a second MOS transistor connected in series to form a first composite transistor having an effective source, gate and drain. The first MOS transistor receives an input of the differential offset comparator circuit at a gate thereof.

Abstract: A two stage low noise amplifier (10) includes a first stage (12) and a second stage (14). The first stage (12) receives an input signal (VIN), performs single to differential conversion on the input signal (VIN), and generates an input differential signal (VA and VB) therefrom. A bias level of the input differential signal (VA and VB) may be adjusted to an optimal bias point of the second stage (14). The first stage (12) provides the input differential signal (VA and VB) to the second stage (14) And provides image rejection without any loss in amplifier gain. The second stage (14) performs image rejection on the input differential signal (VA and VB) and generates an output differential signal (V+ and V−) therefrom. The first stage (12) and stage (14) include a tuning circuit to adjust a center operating frequency of the amplifier (10). The first stage (12) and the second stage (14) receive control signals from a control bus (16) in order to adjust the center operating frequency.

Abstract: A transconductance bias circuit includes: a differential pair having a first transistor M14 and a second transistor M15; a resistor R coupled between a gate of the first transistor M14 and a gate of the second transistor M15, the gate of the first transistor M14 is coupled to a reference voltage node; a third transistor M10 coupled to the first transistor M14; a fourth transistor M11 coupled to the second transistor M15; a fifth transistor M8 coupled to the third transistor M10, a gate of the fifth transistor M8 is coupled to the reference voltage node; a sixth transistor M9 coupled to the fourth transistor M11, a gate of the sixth transistor M9 is coupled to the reference voltage node; a current mirror 22 coupled to the fifth and sixth transistors M8 and M9; and a seventh transistor M6 coupled to the fourth transistor M11, a current in the seventh transistor M6 is equal to a current in the resistor R.

Abstract: In a computer system (10) embodiment, there is included a memory (18) and circuitry (16a) for prefetching information from the memory in response to a prefetch request. The system further includes a system resource (14), wherein the system resource is burdened in response to a prefetch operation by the circuitry for prefetching information. The system resource is also further burdened in response to other circuitry (16b, 16n, 17) using the system resource. The system further includes circuitry (20, 22, 24) for determining a measure of the burden on the system resource. Lastly, the system includes circuitry (26) for prohibiting prefetching of the information by the circuitry for prefetching information responsive to a comparison of the measure of the burden with a threshold. Other circuits, systems, and methods are also disclosed and claimed.

Abstract: A mass data storage device (10) and method for operating it are disclosed. The mass data storage device has a rotating disk memory (14) which has a number of sectors for containing data. A FIFO memory (30) has three memory sections (40-42), each for containing an entire sector of data associated with respective sectors of the rotating disk memory. An ECC unit (34) has random access to any data contained in the FIFO memory (30). The ECC unit (34) is operated to perform error correction on data while the data is contained in the FIFO memory (34).

Abstract: Parameter values of an emulation parameter that is indicative of a data processing operation performed by a data processor are exported from the data processor. In response to detection of a condition wherein a first portion of a first parameter value is identical to a corresponding portion of a second parameter value, the second parameter value and only a remainder portion of the first parameter value other than the first portion are output from the data processor.

Abstract: The present invention provides for improved loopback testing of an electronic communications device. The electronic communications device (50) includes a transmit serializer (16), a transmit output buffer (13), a first phase interpolator (52), a phase locked loop (42), a second phase interpolator (44), a receive deserializer (18), a receive input buffer (15), and phase adjust logic (46). The PLL (42) generates a timing signal in accordance with a reference clock signal (43). In one mode of operation, the transmit serializer (16) transmits data for output through the transmit output buffer (13) in accordance with the timing signal generated by the PLL (42). In another mode of operation, the phase interpolator (52) accepts as input the timing signal generated by the PLL (42).

Abstract: A method for making an isolated NMOS transistor (10) in a BiCMOS process includes forming an N− conductivity type DUF layer (19) in a P conductivity type semiconductor substrate (12), followed by forming alternate contiguous N+ and P conductivity type buried regions (30,26) in the substrate (12). A layer of substantially intrinsic semiconductor material (32) is then formed on the substrate (12) in which alternate and contiguous N and P conductivity type wells (35,36) are formed, respectively above and extending to the N+ and P conductivity type buried regions (30,26). Finally, NMOS source and drain regions (48) are formed in at least one of the P conductivity type wells (35). The method is preferably performed concurrently with the construction of a bipolar transistor structure (11) elsewhere on the substrate (12).

Abstract: An operational amplifier trim circuit architecture that compensates for fabrication process and temperature drift mismatches reflected to the input as input offset voltage errors without additional temperature compensation circuitry. The operational amplifier includes a first input signal and second input signal applied to an input circuit stage. The input circuit stage amplifies the first input signal differentially with respect to the second input stage and generates a differential current which in turn is applied to a first current path and a second current path. The first current path and second current path have well-matched trim circuits. The first current trim applies a trim current to the first current path, and the second current trim applies a trim current to the second current path.

Abstract: A real-time power conservation apparatus and method for portable computers employs a monitor to determine whether a CPU may rest based upon a real-time sampling of the CPU activity level and to activate a hardware selector to carry out the monitor's determination. If the monitor determines the CPU may rest, the hardware selector reduces CPU clock time; if the CPU is to be active, the hardware selector returns the CPU to its previous high speed clock level. Switching back into full operation from its rest state occurs without a user having to request it and without any delay in the operation of the computer while waiting for the computer to return to a “ready” state. Furthermore, the monitor adjusts the performance level of the computer to manage power conservation in response to the real-time sampling of CPU activity.

Abstract: The two-stage power amplifier includes: a first stage transconductor 60; and a second stage having at least two parallel output branches 57-59 supplying current to an output node 89, each output branch has an input coupled to an output of the first stage transconductor 60.

Abstract: A regenerative tie-high, tie-low cell (circuit) that provides unconditionally stable logic (1 and 0) output states used to tie off logic inputs. The circuit of this invention eliminates any current flow through p-channel/n-channel transistor pairs found in many conventional circuits and adds a regenerative transistor 42 to assure rapid response in achieving the proper logic output states. In one preferred embodiment, the circuit consists of only three CMOS transistors 40-42 that reduce the silicon area required, lowers the cost, and improves the overall reliability.

Abstract: A semiconductor processing apparatus (10) is disclosed which includes a process chamber (12) and at least one substrate support (18) disposed within the process chamber (12) operable to support a substrate wafer (20). The semiconductor processing apparatus includes at least one showerhead assembly (14) disposed within the process chamber (12) facing the substrate support (18) and has a showerhead plate (16). The showerhead plate (16) has a plurality of passageways (17) extending therethrough for directing process fluid toward a substrate wafer (20) disposed on the substrate support (18). A blocking assembly (21) is disposed within the process chamber (12), the blocking assembly has an active position (32) between the showerhead assembly (14) and the substrate support (18) to restrict the flow of process fluid between the showerhead assembly (14) and the substrate support (18).

Abstract: A means to minimize physical distortion and modifications in the electrical properties of ferroelectric films incorporated into semiconductor devices is proposed. By introducing crystallographic texture into these ferroelectric films, the piezoelectric coefficient of the material can be minimized, reducing the interaction between a voltage across and mechanical stress on the film. In addition to having low piezoelectric coefficients, rhombohedral lead zirconate titanate films oriented along (111) exhibit low coercive fields and high remnant polarization, increasing their usefulness in layered semiconductor devices.

Abstract: A transient fuse (102) and antenna (110) for detecting charge-induced plasma damage in a device (112). When the transient fuse (102) is placed between the antenna (110) and the device (112), only charge-induced damage during a metal clear portion of an etch occurs in device (112). When the transient fuse (102) is placed between ground and both the device (112) and the antenna (110), charge-induced damage occurring during an overetch portion of the etch can be detected in the device (112).

Abstract: A DC-to-DC converter to convert a first DC voltage to a second DC voltage includes a first switch connected to input the first DC voltage, a second switch, the first switch and the second switch being controlled by an input signal to generate the second DC voltage, the first switch and the second switch being connected to a control reference, and a control circuit to control the delay of the input signal by monitoring the control reference around an optimal delay point.

Abstract: The present invention overcomes the gate leakage drawback existing in advanced CMOS technologies to achieve extremely high-speed analog-to-digital conversion. The circuit and method employ an input offset storage (IOS) technique to calibrate the differential comparator device during an auto-zero cycle. The reference voltage and offset voltages are stored on capacitors coupled to the inputs of the differential comparator device during the auto-zero cycle. A source follower is placed between each capacitor and the inputs to the differential comparator device. The source followers are selected to prevent leakage from the capacitors during a conversion mode. Additionally, switches utilized in feedback loops for auto-zeroing the differential comparator are also selected to prevent leakage of the capacitors in the conversion mode.

Abstract: A package for a flip chip integrated circuit including an interposer with electrical interconnecting for signal, power, and ground contacts. Routing is accomplished on only two conductor layers through the use of selective planes and buses. Multiple power planes are provided on a single conductor level to support circuits having different operating voltages. A unique cavity down BGA package for a flip chip interconnected integrated circuit is provided by adhering the interposer to a thermally conductive stiffener or base, and using solder balls to attach the frame to the base and interposer. The assemblage forms a chip cavity with interconnecting vias to external BGA solder balls terminals located in the perimeter frame.