Abstract: A data processing circuit has an adder unit divided into plural sections. Each section receives a subset of the bits of the operands and generates a subset of the bits of the resultant. A carry multiplexer is disposed between the sections. This carry multiplexer selects one of a plurality of possible carry inputs to the following sections. The data processing circuit may make the specification of the selection of the carry control multiplexers by: the opcode of the instruction; a combination of the opcode and an opcode modification field; an immediate field directly specifying carry control signals; or designation a carry control register which stores the carry control signals. The adder unit may be divided into sections of equal size or of unequal size.

Abstract: A method for generating a plurality of enhanced accuracy current slopes includes providing a plurality of current slopes and summing signals indicative of each of the plurality of current slopes to generate a current slope sum. The method also includes generating an enhanced accuracy current slope sum based on the current slope sum and generating the plurality of enhanced accuracy current slopes based on the enhanced accuracy current slope sum such that each respective ratio between each enhanced accuracy current slope and the enhanced accuracy current slope sum is approximately equal to each respective ratio between each signal indicative of the corresponding current slope and the current slope sum.

Abstract: A device for measuring pressure in a space includes a semiconductor component suitable for measuring pressure that is positioned in the space and that has connecting pads for flip-chip mounting, a support element with a flat surface carrying a pattern of conductors onto which the semiconductor component is attached, and spacer elements in the space between the pattern of conductors and the bonding pads of the semiconductor component such that there is a space between the semiconductor component and the surface of the support elements in which space the pressure equals the pressure to be measured.

Abstract: A differential receiver circuit includes: a current source 20; a differential pair 22 and 24 coupled to the current source 20; a first transistor 26 coupled to a first branch of the differential pair 22 and 24; a second transistor 28 coupled to a second branch of the differential pair 22 and 24, the first and second transistors 26 and 28 are cross coupled; a third transistor 54 coupled in series with the first transistor 26; a fourth transistor 56 coupled in series with the second transistor 28; a fifth transistor 30 coupled in parallel with the first and third transistors 26 and 54; and a sixth transistor 32 coupled in parallel with the second and fourth transistors 28 and 56.

Abstract: Provided is a symmetrical filter that uses a single comparator. In addition to a voltage divider, a current regulator, and a comparator, the filter of the invention provides control logic that turns on or off a pull up switch and/or pull down switch in order to fully charge or fully discharge a capacitor. Accordingly, in one aspect, the invention is a control logic for a symmetrical filter. Furthermore, timing logic is provided to provide for a more rigorous symmetrical filter performance.

Abstract: The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to modify a hold signal for one or more of the plurality of sample and hold subcircuits to thereby reduce timing mismatch between the plurality of sample and hold subcircuits and distortion associated therewith. The present invention also comprises a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit. The method comprises detecting timing mismatch associated with a plurality of sample and hold subcircuits and modifying a hold signal for one or more of the subcircuits.

Abstract: A method and apparatus for supporting multiple bit allocations in a multicarrier modulation system arc disclosed. Hence, symbols being transmitted or received can make use of different bit allocations. By supporting the multiple bit allocations, the multicarrier modulation system is able to support bit allocation on a superframe basis. Also disclosed are techniques for selection and alignment of superframe formats to improve system performance. In the case of data transmission systems involving different transmission schemes, different bit allocations can be used to reduce undesired crosstalk interference.

Abstract: A method and system for controlling data latency in a communication network use a pre-selected portion of the data to identify one of at least two latency paths. The data is transported to a network device (500) through physical channel (502). The network device (500) includes at least two latency paths (506,508), each operable to transport the data through to other parts of the device (500) at an associated rate. In a first aspect of the present invention, data sorter (504) extracts a latency path identifier from the incoming data then provides the incoming data to one of the at least two latency paths (506,508) accordingly. In another aspect of the present invention, the data sorter (504) extracts a indicator from the incoming data which characterizes the incoming data, decodes the indicator to determine which of the at least two latency paths (506,508) to selects, then provides the incoming data to the selected one of the at least two latency paths (506,508).

Abstract: A clock buffer circuit (100) for generating buffered clock signals (CLKI and CLKI_) in response to an external clock signal (CLKX) is disclosed. A first buffer section (102) drives to a first output node (114) between high and low logic levels in reponse the CLKX signal. To reverse the adverse effects of noise on the falling edges of CLKX signal, a boost section (108) and clock generator (106) are provided. In response to low-to-high transitions at the first output node (114) the pulse generator (106) generates a pulse at a pulse output (126). In response to the pulse, the boost section (108) provides additional driving capability for further pulling the first output node (114) to the high logic level. The first output node provides the CLKI_ signal. A second buffer circuit (104) provides the CLKI signal in response to the CLKI_ signal. An enabling section (110) is provided for enabling, or alternatively, disabling the preferred embodiment (100).

Abstract: A high performance unary digital loudspeaker system is disclosed; providing cost-effective and efficient performance, and providing the option to integrate multiple speaker elements or other related circuitry, and comprising a semiconductor substrate (102), an electrode (104) disposed upon the substrate, an insulator element (106) disposed upon the electrode forming a frame of material, an electrically conductive membrane (108) disposed upon the insulator element so as to form a chamber (110) between the electrode and the membrane, the membrane having a flexible support section (112) formed therein, and a control circuit (200) coupled (114, 116) to the membrane and the electrode, and adapted to provide a variable potential therebetween.

Abstract: A method and apparatus for identifying a track (42) of a rotating disk (12) of a mass data storage device (10) uses EPR4 data detection techniques. The values of the encoded track identification indicia are selected so that they have a distance between any two track identification codewords that is larger than the minimum distance of the codeset from which they were selected. The identification indicia (110-113) are read from the disk (12) using a read head (18), and processed using EPR4 data equalization techniques in an EPR4 Viterbi detector (92). The Viterbi detector (92) may have a trellis in which data paths of minimum distance of the codeset from which the track identification indicia (110-113) were selected do not exist. The Viterbi detector (92) may be used also to detect data pulses (64) by switching its mode of operation from a track identification mode to a data detection mode.

Abstract: A computer system (10). The computer system comprises processing circuitry (14) and storage circuitry (24) for storing a plurality of files. The plurality of files include a circuit description file (243) comprising data describing devices and signals in a circuit. The plurality of files also include a plurality of list expressions (244) relating to one of devices, signals, or devices and signals described by the data in the circuit description. Still further, the plurality of files also include a plurality of rules (245). The processing circuitry is programmed to perform various steps. These steps include processing (34) the plurality of list expressions to extract a plurality of lists in response to the circuit description. Each of the plurality of lists comprises a non-negative integer number of elements.

Abstract: A circuit is designed with an estimate circuit (132) coupled to receive a plurality of predetermined signals (416-418) from an external source. Each of the predetermined signals is spaced apart in time. The estimate cit produces a first estimate signal in response to at least one of the plurality of predetermined signals. An averaging circuit is coupled to receive a data signal 420 and at least one of the plurality of predetermined signals. The averaging circuit produces an average signal from the data signal and at least one of the plurality of predetermined signals.

Abstract: Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.

Abstract: A circuit that generates a write precompensation delay signal includes a precoder, a delayed clock pulse selector, a delayed clock pulse generator, and a non-return-to-zero (NRZ) modulator. A master clock signal and serialized data operating at the master clock rate are inputs to the precoder which generates a precoded data signal operating at the master clock rate. The delayed clock pulse selector generates clock pulse selection signals based on the precoded data. The delayed clock pulse generator generates at least two delayed clock signals, selects either none or one of the delayed clock signals according to the clock pulse selection signals, and generates a return-to-zero (RZ) signal whose time periods comprise either a zero if no delayed clock signal is selected or a pulse of the selected delayed clock signal. The NRZ modulator generates the precompensation signal from the RZ signal, and the precompensation signal has a maximum precompensation delay of at least 50% of the master clock time period.

Abstract: A capacitor array is configured to negate or cancel the voltage coefficient of the capacitors within the array, and thus reduce and/or eliminate the voltage coefficient non-linearities present within the A/D converter. In the capacitor array, a first capacitor is suitably configured with at least one additional capacitor in the array such that the charge across the array is linear with respect to an input voltage applied to the input of the array. In addition, the voltage coefficient non-linearities of the first capacitor can be suitably canceled by the inverse voltage coefficient non-linearities of any additional capacitors within the balance of the array, thereby reducing the potential for non-linearities within the A/D converter.

Abstract: A modular tool for forming features in an exposed pad having a pad surface between a bleed groove and an edge of the pad surface in a lead frame including a first tool for forming a bottom of the exposed pad under the pad surface, a second tool coupled to the first tool for forming a side of the exposed pad, and a third tool coupled to the first tool for forming another side of the exposed pad.

Abstract: An exemplary electronic circuit of the present include first and second buffers 34 and 38, which are preferably unity gain buffers. A first switch 36 (e.g., a NMOS transistor or a CMOS transmission gate) is coupled between the output of the first buffer 34 and the first terminal of a capacitor 40. The input of the second buffer 38 is also coupled to the first terminal of the capacitor 40. A second switch 42 is coupled between the second terminal of the capacitor 40 and a first voltage node Va and a third switch 44 is coupled between the second terminal of the capacitor 40 and a second voltage node Vb. This circuit can be used as an integrator in a number of applications.

Abstract: Disclosed are radio frequency (RF) interference cancellation techniques that effectively estimate RF interference to the data signals being received using a frequency domain model, and then remove the estimated RF interference from the received data signals. Improved techniques for digitally filtering multicarrier modulation samples to reduce sidelobe interference due to the RF interference are also disclosed.

Abstract: A method (50) of communicating bit groups between a first DSL modem (M14) and a second DSL modem (M12). The method receives (56) at the first DSL modem a plurality of bit groups (FF1-FF500) from the second DSL modem. Each of the plurality of bit groups comprises a plurality of bit sub-groups (W1-W12), and each of the plurality of bit sub-groups has an order of location. For each of the plurality of bit groups, the method determines (58) whether bits of at least one sub-group having a common order of location comprise at least one erroneous bit. In response to this determination, the method stores (62, 64) in the first DSL modem a record (InMaskBuff) of whether the at least one sub-group having the common order of location comprises at least one erroneous bit. From this record, various other steps (72) may be taken in the preferred embodiment, including suppressing (82) the at least one sub-group from communicating valid information from the second DSL modem to the first DSL modem.