Abstract: Methods for fabricating plastic molded thermally enhanced flip chip packages in which the heat spreaders are assembled in strip format is disclosed, including the first step of providing the heat spreader strip. Inclusion of heat spreaders in strip format allows better automation of the molding process using equipment and fabrication technology known in the industry, and provides a cost effective solution to assembly of high density area array packages. The design of heat spreaders include reduced cross section connecting straps which are readily severed and leave only a small plastic to metal interface for ingress of contamination. Further the designs comprehend either embedded or exposed heat spreaders with methods to hold securely during the molding process.

Abstract: In a 4T SRAM cell, voltage states of nodes during transition to active is boosted to provide stability and allow lower power consumption standby states.

Abstract: Quiescent current drawn by an array of four-transistor loadless static random access memory (SRAM) cells is minimized by using a negative feedback loop to set a reference voltage, for the wordline driver, to a level which reduces the subthreshold current through the pass transistors to a level which is just barely sufficient to reliably retain data.

Abstract: A low EMI bias current generator for cable modem applications has a distributed output stage with a steering input that controls the amount of bias current flowing through each transistor of a differential pair. A pair of resistors acts as a potentiometer controlling the amount of voltage seen across the input of the differential pair. The resistor pair controls the speed of transfer of bias current from one transistor to another such that the current transfer will take the form of a hyperbolic tangent that will allow a very gentle start-up.

Abstract: The invention is a lead frame that has leads formed in two levels during the etching process in which the lead frame is formed. A lead frame form (40), or continuous strip of lead frame material, is coated on two sides with a photo resist material (41,43). Each photo resist coated side is patterned to define leads on the lead frame. The lead patterns (41,43, 42,44) on the two sides are offset from each other so that patterns on one side of the lead frame material alternate with the patterns on the other side of the lead frame material. Both sides of the photo resist patterned lead frame material are etched to a depth exceeding the thickness of a lead. The photo resist (41,43) material is then removed. The resulting lead frame has leads (50-56)that are in two levels, each level having leads offset by a lead width from the other level, but with an effective zero distance between leads horizontally.

Abstract: A digital fractional phase detector is provided to realize a frequency synthesizer architecture that naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase domain. Synchronous logic is provided across a digitally controlled VCO and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information. The digital fractional phase detector is capable of accommodating a quantization scheme to measure fractional delay differences between the significant edge of the VCO output clock and a reference clock by using a time-to-digital converter to express the time difference as a digital word for use by the frequency synthesizer.

Abstract: A body-tied-to-drain transistor having significantly reduced gate delay and being particularly appropriate for large drivers where a series of inverters is used. The basic configuration ties the drain of the transistor to the body of the transistor when the transistor is turned on, and is disconnected when the transistor is turned off.

Abstract: A method to enhance the formation of nucleation sites on at least one narrow silicon structure comprises the step: forming at least one nucleation region (206/208): masking the at least one narrow silicon structure (202) with a mask (302); treating the at least one nucleation region (206/208) to enhance an ability of said region to form C54 nucleation sites; and removing the mask from the at least one narrow silicon structure (202).

Abstract: A method of operating a processor (30). The method comprises a first step of fetching an instruction (20). The instruction includes an instruction opcode, a first data operand bit group corresponding to a first data operand (D1′), and a second data operand bit group corresponding to a second data operand (D2′). At least one of the first data operand and the second data operand consists of an integer number N bits (e.g., N=32). The instruction also comprises at least one immediate bit manipulation operand consisting of an integer number M bits, wherein 2M is less than the integer number N. The method further includes a second step of executing the instruction, comprising the step of manipulating a number of bits of one of the first data operand and the second data operand. Finally, the number of manipulated bits is in response to the at least one immediate bit manipulation operand, and the manipulating step is further in response to the instruction opcode.

Abstract: A method of forming a semiconductor component having a conductive line (24) and a silicide region (140) that crosses a trench (72). The method involves forming nitride sidewalls (127) to protect the stack during the silicidation process.

Abstract: A chemical mechanical polishing method using a modified slurry. A modified slurry is used with high platen rotational speed and high wafer carrier rotation speeds. The endpoint of the polishing process is determined by monitoring the electrical current of the wafer carrier motor.

Abstract: A DSP (10) accesses internal memory using physical addresses and has a internal MMU (19) which allows the DSP (10) to work with a large virtual address space mapped to an external memory (20). The MMU (19) performs the translation between a virtual address and the physical address associated with the external memory (20). The MMU (19) includes a translation lookaside buffer (28) and walking table logic (32) for translating virtual addresses to physical addresses.

Abstract: A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

Abstract: An integrated circuit comprises a first node (11) and a first stage charge pump (510) coupled to the first node (11) and to load circuitry (520). The first stage charge pump comprises a first capacitor (C1) coupled to a first signal source (&phgr;1), a second capacitor (C2) coupled to a second signal source (&phgr;2), a drain (24) of a first n-channel field effect transistor (MN1) coupled to the first capacitor (C1), and a source (20) of the first n-channel field effect transistor (MN1) coupled to the first node (11). A source (36) of a first p-channel field effect transistor (MP1) couples to a second node (12) and a gate (34) of the first p-channel field effect transistor (MP1) couples to the second capacitor (C2). The gate (34) and drain (32) of the first p-channel transistor (MP1) couple to the gate (22) and drain (24) of the first n-channel transistor (MN1), respectively.

Abstract: An FIR decimation filter includes the a shift register (51) including M flip-flops arranged in M/R rows (52, 54, 56, 58) of R bits each, wherein M/R is an integer and R is the decimation ratio of the FIR decimation filter. The shift register has an input for receiving serial digital input information. Half of the rows are sequentially arranged in an upper section and the other half of the rows are arranged sequentially in a lower section. Each row has a left tap and a right tap. The shift register includes a bidirectional shift register in the top row of the lower section. A control circuit (70) controls shifting operations which each shift input data and data present in the shift register (51) by R bits so as to load a new group of R bits into each row.

Abstract: A real-time power conservation and thermal management apparatus and method for portable computers employs a monitor (40) to determine whether a CPU may rest based upon a real-time sample of the CPU activity and temperature levels and to activate a hardware selector(500, 510, 520, 530) to carry out the monitor's determination. If the monitor determines the CPU may rest, the hardware selector reduces CPU clock time (280); if the CPU is to be active, the hardware selector returns the CPU to its previous high speed clock level (330). Switching back into full operation from its rest state occurs without a user having to request it and without any delay in the operation of the computer while waiting for the computer to return to a “ready” state. Furthermore, the monitor adjusts the performance level of the computer to manage power conservation and thermal management in response to the real-time sampling of CPU activity (10) and temperature (24).

Abstract: A circuit is designed with a decode circuit (313-315) having a first output terminal (319). The decode circuit is coupled to receive an address signal (81, 82, 85) having a first voltage range for producing a first output signal having one of a first and second logic levels. An output circuit (307, 309) is coupled to receive the first output signal and a power supply signal. The output circuit produces a second output signal having a second voltage range. A first latch transistor (301) is coupled to receive the second output signal. The first latch transistor is arranged to couple the first output terminal to a voltage terminal (209) in response to one of a first and second logic state of the second output signal. A second latch transistor (317) is coupled to receive the second output signal.

Abstract: An improved design and method of a digital decimation and interpolation filter for a multi-bit input signal, reduces the buffer requirement during a decimation operation and relieves the processing bottleneck during an interpolation operation through the use of transposition of an FIR filter structure having time-varying coefficients. The design includes an input lead (120), a multiplier (122), a accumulator (132), a memory (128), a shift register (132), an output buffer (138) and a sequencer (140). The input lead receives the digital input signal. The multiplier (122) having a first and second multiplier input terminal coupled to the input lead (120) at its second multiplier terminal receives the digital input signal. The memory (128), having stored coefficient sets, is coupled to the first multiplier input terminal. The sequencer (140), coupled to the memory (128) and the output buffer (138), transfers each coefficient set to the first multiplier input terminal.

Abstract: A DC-DC converter circuit includes a transformer with a resonate filter or snubber connected at a primary side and a switch for controlling operation of the converter. A secondary side of the transformer includes self-driven synchronous rectifiers and an output filter. Transistors are provided at the gates leads of the rectifiers and themselves are provided with a fixed voltage at their gates so as to clamp the peak voltages across to the rectifiers.

Abstract: An LDMOS device (10, 20, 50, 60) that is made with minimal feature size fabrication methods, but overcomes potential problems of misaligned Dwells (13). The Dwell (13) is slightly overstated so that its n-type dopant is implanted past the source edge of the gate region (18), which permits the n-type region of the Dwell to diffuse under the gate region (18) an sufficient distance to eliminate misalignment effects.