Abstract: A hard disk drive system (10) includes a rotating magnetic disk (16), and a support arm (22) which is supported for movement relative to the disk under control of a voice coil motor (21). a microactuator (26) supports a read/write head (27) on the support arm for movement relative thereto a control arrangement (13) controls the voice coil motor and the microactuator in response to position information (31), which is read by the read/write head from the disk and which indicates the position of the read/write head relative to the disk. The system is free of a sensor for detecting the actual position of the support arm relative to the read/write head or the disk.

Abstract: A method to provide automatic content-based video indexing from object motion is described. Moving objects in video from a surveillance camera 11 detected in the video sequence using motion segmentation methods by motion segmentor 21. Objects are tracked through segmented data in an object tracker 22. A symbolic representation of the video is generated in the form of an annotated graphics describing the objects and their movement. A motion analyzer 23 analyzes results of object tracking and annotates the graph motion with indices describing several events. The graph is then indexed using a rule based classification scheme to identify events of interest such as appearance/disappearance, deposit/removal, entrance/exit, and motion/rest of objects. Clips of the video identified by spatio-temporal, event, and object-based queries are recalled to view the desired video.

Abstract: A method of forming an ultra-thin gate oxide (14) for a field effect transistor (10). The gate oxide (14) is formed by combining an oxidizing agent (e.g., N2O, CO2) with an etching agent (e.g., H2) and adjusting the partial pressures to controllably grow a thin (˜12 Angstroms) high quality oxide (14).

Abstract: A mixed signal CODEC including an improved sigma-delta ADC (20) which limits input signals into a switched capacitor configuration and avoids adding circuit overhead in the signal path is disclosed herein. Additionally, it avoids overshoot and settling problems. This sigma-delta analog-to-digital converter (20), having an input signal and an output signal, includes a switch (sw1), a clipping circuit (21), and a known sigma-delta ADC (34). It solves the clipping signal problem by limiting the signal right at the input of the sigma-delta ADC (34). The clipping circuit (21) couples to the switch (sw1) and the sigma-delta ADC (34) for switching the voltage applied to the sigma-delta ADC between the input signal (vin) and at least one threshold voltage (Vn and Vp).

Abstract: A protection circuit is designed with an external terminal (300), a reference terminal (126) and a substrate (342). A semiconductor body (338) is formed by an isolation region (332, 340) formed between the substrate and the semiconductor body, thereby enclosing the semiconductor body. A plurality of transistors is formed in the semiconductor body. Each transistor has a respective control terminal (354) connected to a common control terminal (321) and a respective current path connected between the external terminal and the reference terminal. A capacitor (314) is connected between the semiconductor body and the external terminal. A resistor (318) is connected between the semiconductor body and the reference terminal.

Abstract: The objective of the invention is to provide a DSP that can perform hold testing, which evaluates the halt state of the DSP core, during DSP core self-testing. DSP circuit 2 has input scheduler 8 that outputs restart signals to halt terminal HALT, which controls operation halt/restart for the of DSP core 4, when a fixed time has elapsed after operation of DSP core 4 has halted during hold testing, so the stopped DSP core 4 can be restarted. Thus, the internal state of DSP core 4 when operation restarts, can be recognized by the DSP core 4 itself, so it will be possible to implement hold testing that evaluates whether or not the DSP core 4 has correctly halted operation.

Abstract: Contacts for an electronic device are formed by providing a substrate (12) that has at least two access line structures (16) for a memory array (14) and a periphery structure (20) for a peripheral circuit (18) to the memory array (14). A first insulative layer (40) is formed outwardly of the substrate (12), the access line structures (16), and the periphery structure (20). A contact area of the periphery structure (20) is exposed through the first insulative layer (40) while maintaining the first insulative layer (40) over at least a contact overlap portion (48) of the access line structures (16). A second insulative layer (60) is formed outwardly of the substrate (12), the access line structures (16), the periphery structure (20), and the first insulative layer (40).

Abstract: A circuit coupled to receive a sequence of signals is designed with a multiplication circuit (416, 420) coupled to receive a first signal, a second signal and a complex conjugate of the first signal. The second signal follows the first signal in time. The multiplication circuit produces a first product sequence of the first signal and the complex conjugate and a second product sequence of the second signal and the complex conjugate. A summation circuit (424, 426) is coupled to receive the first product sequence and the second product sequence. The summation circuit produces a first sum of the first product sequence and a second sum of the second product sequence.

Abstract: A method for fabricating a memory array includes fabricating a first portion (110, 310, 510) of a memory array on a first side (14, 214, 414) of a substrate (12, 212, 412). A second portion (150, 350, 550) of the memory array is fabricated on a second, opposite side (16, 216, 416) of the substrate (12, 212, 412). The first portion (110, 310, 510) and the second portion (150, 350, 550) of the memory array are coupled to each other through the substrate (12, 212, 412).

Abstract: An integrated circuit including a DRAM is disclosed, wherein the DRAM includes a memory array including a plurality of pass gate transistors and a plurality of memory elements. The pass gate transistors include a gate material selected to provide a substantially near mid-gap work function or greater. The DRAM also includes a peripheral area including a plurality of logic transistors. In a preferred embodiment the pass gate transistors are silicon-on-insulator transistors.

Abstract: This invention is a testing technique for an electronic circuit such as an integrated circuit. The electronic circuit includes a JTAG test access port and at least one testable embedded core circuit having its own JTAG compliant second test access port. A test access port controller and a programmable switch control testing of the electronic circuit. An internal state in the test access port controller controls the switch state of the programmable switch. The programmable switch is controlled to selectively connect the first test access port to the embedded core circuits. When an embedded core circuit is connected for test, the test access port controller remains responsive to the first test access port and operates in a set of snoopy states corresponding to the state of the embedded core circuit under test. The test access port controller can regain control of the first test access port and disconnect all of the embedded core circuits when in snoopy states.

Abstract: A semiconductor package substrate for assembling an integrated circuit chip operable at fast ramp rate signals and clock rates, comprising an insulating support having a region for attaching said chip; a pattern of electrical interconnections, disposed on said substrate in one metallization level and operable for transmitting waveforms; and a low pass filter for removing unwanted high frequency components from said transmitted waveforms, comprising a network of inductors and capacitors formed within said one metallization level and positioned substantially within said substrate region for chip attachment.

Abstract: Deposition of titanium over fluoride-containing dielectrics requires the use of a method of passivation to prevent the formation of TiF4, which causes delamination of the metallization structure. Disclosed methods include the formation of layers of Al203, TiN, or Si3N4.

Abstract: A mobile communication system is designed with an input circuit coupled to receive a first plurality of signals (rj(i+&tgr;j), i=0−N−1) during a first time (T0-T1) from an external source and coupled to receive a second plurality of signals (rj(i+&tgr;j), i=N−2N−1) during a second time (T1-T2) from the external source. The input circuit receives each of the first and second plurality of signals along respective first and second paths (j). The input circuit produces a first input signal (Rj1) and a second input signal (Rj2) from the respective first and second plurality of signals. A correction circuit is coupled to receive a first estimate signal (&agr;j1), a second estimate signal (&agr;j2) and the first and second input signals. The correction circuit produces a first symbol estimate (S1) in response to the first and second estimate signals and the first and second input signals.

Abstract: A segmented digital-to-analog converter includes: upper segments 200, 210, and 220; a thermometer decoder 400; a randomizing circuit 410 coupled between the thermometer decoder 400 and the upper segments 200, 210, and 220 for randomizing an output of the thermometer decoder 400; a divider location selector circuit 420 coupled between the randomizing circuit 410 and the upper segments 200, 210, and 220 for choosing a selected segment from the upper segments 200, 210, and 220; and lower segments 225 coupled to the selected segment.

Abstract: A system for dynamic adaptation of wireless communication between a Mobile Station (11) and a Base Station (13) wherein the transmitted frame from the Mobile Station includes a convolutionally coded portion containing a down-link measurement bit and a repetition code identifying the codec mode of the frame. The transmitted frame from the Base Station (13) includes a codec mode command signal for the Mobile Station (11) in the convolutionally encoded portion and the repetition code identify the codec mode of the down-link frame. The Base Station (13) includes means for analyzing the quality of the up-link frame and means from the received down-link measurement bit for determining the down-link quality.

Abstract: A method and a system for performing memory-based convolutional interleaving are disclosed. According to the disclosed method, delay lines (DL) are paired with one another within rows of a memory, where the pairing is effected so that the sum of the delay of the paired delay lines is constant over the rows. Both in transmission and in receipt of the interleaved data packets, one or more data packets are read from the oldest location of one of the paired delay lines, with one or more data packets from a received vector being written into this delay line; this reading and writing is repeated for each of the rows of the memory, advancing in a first direction. The process of reading and writing is then repeated for the other delay line in each of the rows of the memory, advancing in the opposite direction. The pairing of the delay lines (DL) in each row of the memory permits efficient implementation of convolutional interleaving, with a minimum of overhead processing required.

Abstract: The marking of identification and orientation information along the edge (E) of a semiconductor wafer (20, 20′) is disclosed. The information may be marked by way of laser marking at one or more locations (10) along a flat portion (14) or bevel (12t, 12b) of the edge (E) of the wafer (20, 20′). The wafer marking (10) may be encoded, for example by way of a 2-D bar code. A system (30) for reading the identification information from wafers (20, 20′) in a carrier (32) is also disclosed. The system (30) includes a sensor (36) for sensing reflected light from the wafer markings (10) along the wafer edge (E), and for decoding identification and orientation therefrom. A motor (38), under the control of feedback (RFB) from the sensor (36), rotates the wafers (20, 20′) by way of a roller (39) until the wafer marking (10) is in view by the sensor (36). A processing system (40), which includes a rotatable chuck (41) upon which the wafer (20, 20′) is placed, is also disclosed.

Abstract: A data file (22) having a plurality of frames is received, with each frame having a syncword. A data string (52) including a plurality of potential syncwords (54) is identified in the data file (22). One of the potential syncwords (54) is randomly selected. A subsequent potential syncword address is determined based on the selected potential syncword (54). Whether a subsequent potential syncword exists at the subsequent potential syncword address is determined. The data file (22) is decoded based on the subsequent potential syncword in response to the subsequent potential syncword existing at the subsequent potential syncword address.

Abstract: A system for producing metal gate MOSFETs having relatively low threshold voltages is disclosed, comprising the steps of forming 200 a gate oxide layer on a semiconductor substrate, forming 210 a dummy gate on the substrate, removing 260 the dummy gate after further processing and depositing 270 a lower metallic gate material on said gate oxide; treating 280 the semiconductor device with a reducing gas immediately after deposition of the lower metallic gate material, and depositing 290 an upper gate metal over the lower gate material.