Abstract: A power amplifier controller (45) for a wireless communications device (10), such as a wireless telephone, is disclosed. The power amplifier controller (45) has includes controllable bias current sources (56, 58) coupled to Schottky diodes (60), which are coupled to power amplifiers (50) to sense their power output. The controllable bias current sources (56, 58) selectably apply one of multiple available bias currents (I1, I2) to their corresponding Schottky diodes (60F, 60R). Timing and control circuitry (62) in the power amplifier controller (45) receives a desired power level signal (DESPWR), and control switches (SW1, SW2) in the controllable bias current sources (56, 58) to apply a bias current (I1, I2) responsive to the level of power indicated by the desired power level signal (DESPWR). The power detected by Schottky diodes (60F, 60R) is applied to a summing adder (65), from which a control signal (VAPC) is derived and used to control the output of the power amplifiers (50).

Abstract: The present invention includes an improved switching device (400) which operates in a shared media environment. The switching device (400) in accordance with the present invention includes a tag header processing means (402) operable to insert a tag header into frames that enter the switching device (400) without a tag header and CRC processing means (404) operable to calculate a CRC for the frame excluding the tag header for use while the frame is being processed within the switching device (400). The tag header processing means (402) is further operable, when the internal switch processing of the frame is completed and the frame is ready to be transmitted, to determine whether or not the frame should be transmitted without a tag header and removing the tag header if it is not.

Abstract: High performance digital transistors (140) and analog transistors (144) are formed at the same time. The digital transistors (140) include pocket regions (134) for optimum performance. These pocket regions (134) are partially or completely suppressed from at least the drain side of the analog transistors (144) to provide a flat channel doping profile on the drain side. The flat channel doping profile provides high early voltage and higher gain. The suppression is accomplished by using the HVLDD implants for the analog transistors (144).

Abstract: A memory device (10) includes a memory array (12) having storage units (14) arranged in a plurality of rows (16). A row decoder (18) receives address information and determines which of the plurality of rows (16) to enable. According to the determined row (16), a row selector (20) drives the storage units (14) associated with the determined row (16) to provide their outputs onto respective bitlines (34) for identification by a bitline sensor (22). If the received address information indicates an out of range address that does not identify any of the plurality of rows (16) of the memory array (12), an out of range decoder (24) provides such determination to drive an out of range selector (26) to enable storage units (30) arranged in a single row (32) of a bitline driver (28). Outputs from the storage units (30) are applied to the respective bitlines (34) during an out of range address occurrence to prevent the bitlines (34) from being placed in an undesirable floating state.

Abstract: A 6T CMOS SRAM cell (100) that increases process margins for a given cell area The cell (100) comprises a pair of cross-coupled inverters (102, 104). Each inverter (102, 104) comprises a p-channel pull-up transistor (106, 108) and a n-channel pull-down transistor (110, 112). The p-channel pull-up transistors (106, 108) are offset in both the vertical and horizonal directions from the n-channel pull-down transistors (110, 112).

Abstract: A sensor control and data analysis system (100) for detecting and analyzing various (bio)chemical properties of a given sample substance (107) using an integrated SPR sensor (50) or other miniaturized sensor configuration. In one embodiment, raw sensor data from the sensing device (105) is transferred to a remote processing system (111), such as a desktop computer, having a display (125), keyboard or other user control and data entry device (123), internal storage area (127), internal microprocessor (117) and a communications means (129). The processing system (111) runs a software application program (115) that receives the raw sample data and perform qualitative and quantitative analysis to render meaningful information about the sample substance.

Abstract: A method of correcting the output of a rotary displacement transducer so as to remove spin frequency noise error. For each revolution of the transducer, a series of transducer output values is accumulated. Each output value represents a time interval between transducer pulses. These output values are used to calculate sin and cosine values of a sin wave and cosine wave having a period determined by the transducer resolution. From the sin and cosine waves, a quadrature and an inphase value are obtained, and the latter values are used to calculate magnitude and phase values of a correction sin wave having the same transducer periodicity. The magnitude and phase values are used to calculate a correction value for each transducer output value.

Abstract: An unregulated inductorless direct current to direct current converter comprising a first voltage-to-current converter configured to convert a first voltage to a first current and a second voltage-to-current converter configured to convert a second voltage to a second current. A regulation circuit is coupled to the first and second voltage-to-current converters and configured to generate an output current proportional to the difference between the first and second currents. Also a variable frequency oscillator is coupled to the regulation circuit, the oscillator receiving as a control current the output current therefrom and outputting a clock signal having a frequency proportionate to the control current. The converter further comprises an output stage coupled to receive the clock signal and receiving an input voltage and outputting an output voltage, the output voltage and the input voltage having a ratio that is determined by the clock signal.

Abstract: A dicing saw blade assembly with parallel blades separated by a spacer and attached to a single spindle on an automated dicing saw, is applicable to precisely separating CSP or MCM devices which have been fabricated on a polymeric substrate. Two parallel cuts are made simultaneously in the scribe streets of the substrate to separate the flip chip devices. The substrates are diced from the bottom side, thereby allowing use of thin blades for separating devices having relatively thick chips, as well as chips with attached heat spreaders.

Abstract: A method of modeling and enhancing the print quality of digital printing, including both electrophographic printing and photofinishing. Pixels are printed with a device such as a DMD, whose pixels provide a steep-sided intensity versus displacement curve of each light spot on the image plane. Holes placed in the pixel can be used to place a dip in the top of the curve, a feature especially useful for electrophotographic printing. The effect of this hole on the image plane can also be flattened, a feature than may be especially useful for photofinishing. The steep-sided intensity curve facilitates the ability to model and predict pixel size.

Abstract: Failsafe interface circuits are provided for an integrated circuit having a core logic section providing a signal to, or receiving a signal from, a bond pad connection. The interface circuits employ high voltage tolerant, extended drain devices in circuit arrangements which insure that the stress of a failsafe event is only exhibited by the extended drain devices. A failsafe event is defined as a bond pad voltage which exceeds the supply voltage of the integrated circuit plus the threshold voltage of the transistors within the integrated circuit. Both failsafe output driver circuit and failsafe receiver circuit embodiments are provided.

Abstract: A frequency synthesizer (500) includes a DDFS (502) and a PLL loop (526). The oscillator frequency signal (516) is used to create the DDFS clock signal (514), fCLK that acts as a system clock for the DDFS (502). With the phase/frequency state of the DDFS being adjusted based on a comparison of the DDFS system clock signal (514) with a frequency reference signal (520), fREF. The DDFS system clock signal (514) is further divided by a divider (512) to establish an update clock signal (528), fupdate. The output of the DDFS and the update clock signal (528) are compared by a phase/frequency detector (504). The output signal of the PFD (504) is preferably filtered by a loop filter (506) before using it as a tuning signal (522) for the DCO (508). The principle of bootstraping ensures that the synthesizer (500) is synchronous and every clock is derived from the same source.

Abstract: Circuitry for identifying digital data packets, each comprising a useful signal and a header signal containing data pertaining to the contents of the useful signal is provided. The circuitry includes a means (30) for extracting data from each header signal, which data is representative of a corresponding useful signal, a means for storing reference data in a memory, at addresses each corresponding to a packet type, and a means for comparing the data extracted from each header signal with said reference data stored in memory, and for the delivery, to a data processing unit (32,34), of an address signal indicating the nature of the corresponding packet. The data storage means and the comparison means preferably employ an associative memory (38) adapted to ensure the simultaneous comparison of the data extracted from each header signal with the reference data stored in memory.

Abstract: A method and circuit for improving the aperture distortion in parallel A/D converters by reducing the delay mismatch in the sample-and-hold portion of A/D converter circuit. The technique involves generating two complementary clocks, Q and {overscore (Q)}, from a single master clock and then gating these two clocks, in a random fashion, with the original master clock in order to significantly reduce the delay mismatch in the circuit. This approach involves the random selection of gated switches from dual banks each containing a plurality of parallel switches, thereby compensating for aperture error by converting any systematic aperture mismatch between the sampling clocks into random noise spread over the frequency band. High speed A/D converters incorporating the techniques of this invention will provide superior performance in digital audio, digital video, and many other digital applications.

Abstract: A hermetically cold weld sealed package and method for sealing where a metal seal member 28 is placed along the edge of a base 36, an organic sealant 26 is placed along the outside of the base adjacent the metal seal member 28, and a lid 30 is placed over the base 36 to create a hermetically sealed cavity 46. The process takes place at room temperature environment in an inert environment, and on heating of the metal sealing member 28 is required. The shrinkage of the organic sealant 26 during curing applies pressure to the metal seal member 28, enhancing the effectiveness of the hermetic seal.

Abstract: The invention is a method of forming the art work for chemically etching that produces uniform through-etch and lateral-etch. The artwork that defines the pattern to be etched utilizes lines equal to the narrowest feature that is to be etched. Rather than etch away large areas, section are removed by etching by cutting them out of the material that is being etched. The artwork or pattern is designed with the same compensation factors throughout the entire pattern and the etch rate will be completely uniform for the entire pattern.

Abstract: A CMOS bus switch (20) having undershoot protection circuitry (22) to help prevent data corruption when the switch is open and the buses (A,B) are isolated from one another. A bias generator (30) sets a voltage (Bias) referenced to ground which allows the active pull-up clamp to turn on when the bus voltage goes negative. This clamp attempts to counteract the undershoot voltage and limit the Vgd or Vgs of the N-channel pass transistor (MN1) and the Vbe of the parasitic NPN transistor. Since the active pull-up clamp circuit is also over-voltage tolerant, this invention will work equally well in high, low, and mixed voltage systems.

Abstract: A method of increasing the cycle life of a thermostatic disc element for use in a disc assembly used in thermostatic switches in which a weld slug is used to weld the disc element to the disc assembly thereby causing a heat affected zone of the disc element comprising the step of engaging the surface of the disc element opposite the surface adjacent the weld slug with a fulcrum member at a location spaced from the heat affected zone so that upon reversal of the curvature of the disc element, the disc element will bend about the fulcrum member at a location removed from the heat affected zone.

Abstract: A field emission display apparatus has an emitter plate 2 having a plurality of column conductors 9 intersecting a plurality of row conductors 6, and electron emitters 5 at the intersection of each of the row and column conductors. An anode plate 62 is adjacent to the emitter plate 2, the anode plate 62 comprising conductive stripes 50 which are alternately covered by material luminescing in the three primary colors. The conductive stripes 50 covered by the same luminescent material are electrically interconnected to form comb-like structures corresponding to each of the colors. The anode plate 62 contains an active region 58 and the buses 82, 84, 86 have a non-uniform width.

Abstract: A linecard (175) permits an increased rate connection between a subscriber (15) and a service provider (40) over the PSTN (50) includes an analog interface (152) a digital interface (165) coupled to the digital backplane (170) to the service provider's host server (34), a conversion circuit (258) interspersed between the analog interface (152) and the digital interface (165), and a linecard microcontroller (300) configured to request bandwidth on the backplane (170) A linecard (175) incorporates a codec (250) with a code recognition mechanism (200) to monitor the Pulse Code Modulated (PCM) input from the provider. The code recognition mechanism (200) provides a way to dynamically allocate and deallocate timeslots on the backplane (170).