Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: A multi-rate data receiver includes a decoding section for processing the received encoded data symbols via multiple paths to make a determination as to the rate of the received data. A statistical analysis is made of the incoming data prior to decoding, and rate selection made among one of the multiple highest rates. If the determination is not that the data is associated with the highest rate, the data is processed through multiple parallel decoding paths and the decoded data on the output thereof evaluated to determine which of the multiple paths is acceptable and associated with the incoming data rate.

Abstract: A circuit (50) and method are presented for demodulating servo bursts (40-45) detected from a data medium (12). The circuit (50) includes an A/D converter to receive the detected servo bursts to convert the servo bursts (40-45) into digital data words at predefined sample times (48). A peak detector (52) determines respective peaks of the digital data words. A circuit (72, 74) weights the peaks of the digital data words with predefined weights, and a circuit (76) accumulates the weighted peaks. Circuits 88 and 90 detect the maximum and minimum weighted peak values, respectively, from the incoming data stream. A circuit (78) determines a sum of the weights applied to the digital data words. Circuits 96 and 98 store the weight values which correspond to the peak values detected by circuits 88 and 90, respectively, and a circuit (80) divides the accumulated weighted peaks by the sum of the weights.

Abstract: A system (100) for interfacing hardware and software components in a simulation system is disclosed. The present invention includes at least one cell (110) having a model access and control hub (140) and at least one block (142) within the cell (110) connected to the model access and control hub (140). The block (142) executes a command (196) sent by the model access and control hub (110). The present invention also includes an interprocess communication device (104) including shared memory (105) coupled to the model access and control hub (140). The shared memory (105) communicates the command (196) to the model access and control hub (140). The present invention also includes a debugger (106) coupled to the interprocess communication device (104) that issues the command (196) to the model access and control hub (140) via the shared memory (105), and receives information from the model access and control hub (140) via the shared memory (105).

Abstract: Integration of dual voltages on a single chip can be accomplished with a minimum of extra masks by optimizing only the MDD implant of the peripheral transistors, while other implants remain the same for both transistor types. This meets lifetime specifications without unnecessary expense.

Abstract: A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.

Abstract: Offers a filter circuit in which the dedicated capacitor surface area is small and in which a dedicated process just for capacitor formation is unnecessary. The filter circuit of this invention is an active filter circuit wherein an operational amplifier AMP1 and capacitors (C1, C2) are formed on the same semiconductor substrate. The capacitors (C1, C2) are constructed from an insulated gate field effect transistor wherein the mutually connected source and drain forms one of the electrodes, the gate forms the other electrode, and the gate insulating film is used in the capacitor dielectric film. For capacitor C1, a DC bias means (DC bias circuit V2) that applies a prescribed DC bias is connected between the electrodes of the said capacitor. A DC bias means can also be provided at capacitor C2, but here, it can be omitted by just increasing the DC level of the input signal Vin just a prescribed level.

Abstract: The recognition of hands-free speech in a car environment has to deal with variabilities from speaker, microphone channel and background noises. A two-stage model adaptation scheme is presented. The first stage adapts speaker-independent HMM seed model set to a speaker and microphone dependent model set. The second stage adapts speaker and microphone-dependent model set to a speaker, microphone, and noise dependent model set, which is then used for speech recognition. Both adaptations are based on maximum-likelihood linear regression (MLLR).

Abstract: A capacitor structure (100) including first and second capacitor plates (102, 106) insulatingly spaced from each other by a capacitor dielectric (102). A first set of conductive posts (301) electrically couple to the first capacitor plate (102) and extend away from the capacitor dielectric (104). A first conductive structure (302) comprising a material with lower resistivity than the first capacitor plate (102) is electrically coupled to the first set of conductive posts (301). In a preferred embodiment, a second set of conductive posts (501) are electrically coupled to the second capacitor plate (106) and extend away from the capacitor dielectric (102). A second conductive structure (503) is electrically coupled to the second set of conductive posts (501).

Abstract: A cascode H-bridge circuit with particular application to magnetic recording write driver circuits. The present invention avoids the process dependent limitations placed on the head voltage swing in the H-bridge circuits of the prior art. Whereas the circuits of the prior art attempt to increase head voltage swing by minimizing device voltage drops in the current path, the present invention inserts cascode transistors in the current path that have less than a one-volt voltage drop when active, yet allow the circuit to operate under a higher voltage supply with roughly twice the head voltage swing available in the same process in the prior art. By implementing a cascode configuration, the present invention is able to support head voltage swings in excess of the switch breakdown voltage (BVCEO) without failure of the switches in the “off” state.

Abstract: A controllable ring oscillator clock circuit includes a plurality of ring oscillator stages disposed in a linear chain. Each stage has a latch that determines if this stage is the last stage in the ring. In a propagate state of the latch the ring pulse is sent to the next stage. In a return state of the latch the ring pulse is returned to the prior stage. The latches are programmed like a shift register. A more command transfers the propagate state to the next stage. This increases the length of the delay line and thus decreases the oscillator frequency. A less command transfers the return state to the prior state, decreasing the ring delay and increasing the oscillator frequency. In the preferred embodiment the delay stages are deployed as even and odd pairs with only the even or the odd stages changed at one time. This enables a simple structure because the pairs operate like a master-slave flip-flop, that is the data can move only a single stage at a time.

Abstract: A method and apparatus for resist strip. Wafers (108) with a patterned resist formed thereon are placed in a carrier (104) in a process chamber (102). An ozonated deionized water mist (120) is sprayed on the surface of wafer (108). The ozonated deionized water mist (120) strips the resist and removes the resist residue without the use of hazardous chemicals. The ozonated deionized water mist (120) may be formed in an atomizer that mixes deionized water (116) with ozone (118). The ozonated deionized water mist (120) is then sprayed onto the wafers (108) while the wafers are being rotated.

Abstract: Method and apparatus for electrically interconnecting a sensor (104) in a beverage dispensing apparatus (102) to a sensor control system contained within a separate unit concurrent with attachment of said beverage dispensing apparatus to said separate unit are disclosed, comprising locking members (114) disposed on the beverage dispensing apparatus, a base plate (200) on the separate unit having receptacles (210) adapted to matably engage and align the beverage dispensing apparatus, a plurality of base plate conductor members (212), disposed on the lower surface of the base plate and electrically coupled to the sensor control system, a plurality of dispenser apparatus conductor members (118), electrically coupled (202) to the sensor and disposed on an upper surface (112) of the beverage dispensing apparatus such that as the beverage dispensing apparatus is matably engaged with the base plate the conductor members are brought into alignment and communicative contact.

Abstract: A method of modem communications between first and second modems (10, 20k) over a communications facility (TWP). The method operates the first modem (20k) to issue communications to the second modem (10) over the communications facility. These communications comprise a plurality of subchannel signals (n). The method also operates the second modem to perform various steps. In one of these steps, the second modem converts (33) the communications from time domain communications to frequency domain communications, where the frequency domain communications signals comprise a plurality of subchannel signals. Each of these plurality of subchannel signals comprises an amplitude portion and a phase portion. In another of these steps, the second modem equalizes (36) the amplitude portion of each of the plurality of subchannel signals using fixed gain factors (GE(n))corresponding to each of the plurality of subchannel signals.

Abstract: The opamp with common mode feedback bias includes: a first differential pair M1 and M2 having first and second inputs; active load devices M3 and M4 coupled to the first differential pair M1 and M2; a common mode feedback circuit 20 coupled to the active load devices M3 and M4 for controlling the active load devices M3 and M4; a second differential pair M18 and M19 having a first input coupled to the first input of the first differential pair M1 and M2 and a second input coupled to the second input of the first differential pair M1 and M2; and current drivers M22 and M23 having control nodes coupled to the second differential pair M18 and M19 and outputs coupled to the active load devices M3 and M4.

Abstract: A multichip semiconductor assembly comprising a semiconductor chip stack comprising first and second chips, each having an active surface including an integrated circuit and a plurality of input/output contact pads; a leadframe for interconnecting semiconductor integrated circuits having a plurality of leads, portions of said leads comprising undulating patterns and a surface metallurgy for promoting solder wetting, said leadframe being disposed between said first and second chips, and said active surface of said first chip positioned in front of said active surface of said second chip; and connections between each of said contact pads of said first chip to one of said leads, respectively, and between each of said contact pads of said second chip to one of said leads, respectively, said connections comprising solder balls, whereby the connections to at least one of said leads are common between said first and second chips.

Abstract: An emulation parameter indicative of a data processing operation performed by a data processor is exported from the data processor. The parameter value is provided as a plurality of digital bits. After determining that the bits of a first group within the plurality of bits all have the same bit value and that a predetermined bit within a second group of the plurality of bits has a bit value equal to the bit value of the bits of the first group, only the second group of bits is output from the data processor without outputting the first group of bits.

Abstract: In producing data processor emulation information, program counter values used by a data processor are provided in a program counter trace stream, and a synchronization marker is inserted into the program counter trace stream. Trace information indicative of a data processing operation performed by the data processor is also provided, and a program counter value that corresponds to the data processing operation is identified. In this identification, the corresponding program counter value is expressed as an offset which indicates a number of program counter values in the program counter trace stream by which the corresponding program counter value is offset from the synchronization marker in the program counter trace stream.

Abstract: Emulation information including emulation control information and emulation data is exported from a data processor by arranging the emulation information into information blocks, and outputting a sequence of the information blocks from the data processor. Some of the information blocks of the sequence have relative proportions of emulation control information and emulation data that differ from the relative proportions of emulation control information and emulation data in other blocks of the sequence.

Abstract: A transistor 10 is formed on an outer surface of a substrate 12. The transistor comprises a floating gate 18 and a control gate 20. An outer encapsulation layer 22 and sidewall bodies 26 and 28 comprise silicon nitride that is deposited in such a manner such that the material is transmissive to ultraviolet radiation. In this manner, the sidewall bodies 26 and 28 and the layer 22 can be used as an etch stop during the formation of a drain contact 38. These layers will also permit the transmission of ultraviolet radiation to the floating gate 18 to enable the erasure of floating gate 18.