Abstract: A dynamic random access memory (DRAM) cell and associated array are disclosed. In a first embodiment, the DRAM cell (300) includes a storage capacitor (304) and a pass transistor (302). The pass transistor (302) is formed within a silicon mesa (310), and includes a source region (316), drain region (318) and channel region (320). The channel region (320) is formed below a furrow (322) that is inset with respect to the top surface of the silicon mesa (310). The channel region (320) has a smaller thickness than that of the source region (316) and drain region (318). A top gate (314) is disposed over the channel region (320). Due to the reduced thickness channel region (320), greater control of the operation of the pass transistor (302) is provided, including an off state with reduced source-to-drain leakage. The greater thickness of the source region (316) and drain region (318) (relative to the channel region (320)) provides greater immunity to the adverse effects of contact spiking.

Abstract: Video compression coding with partitioning of data into motion vector data and texture data with reversible Golomb-Rice type codes for the data. Resynchronization markers separate the data types, and the reversible coding permits decoding in both forward and backward directions to minimize data discarded due to errors.

Abstract: Driver circuitry (300) is disclosed, incorporating feedback circuitry (310) inter-coupled with reference circuitry (348) to equalize the voltage level of an output (328) with a reference voltage source (320) in the reference circuitry; where the driver circuitry comprises a first transistor (340) having a first terminal coupled to a voltage source (342), a second terminal coupled to an input (336), and a third terminal coupled to a resistor (344), a second transistor (338) having a first terminal coupled to ground (332), a second terminal coupled to an input (334), and a third terminal coupled to a resistor (346), a third transistor (318) having a first terminal coupled to the output, a second terminal (326) coupled jointly to the resistors, and a third terminal coupled to ground, and a resistor (330) coupling the output to a voltage source (306).

Abstract: An assembly for generating a consecutive count includes an n-stage binary counter (24) incrementable by counting pulses in successive cycles and an EEPROM (10) in which an item of information representing the count achieved in each case is stored in the pauses between the cycles. The EEPROM (10) comprises n+1 memory cells. A control circuit (36) is provided causing the contents of the n−1 stages of the binary counter (24) assigned to the most-significant bits to be stored in the n−1 first memory cells of the EEPROM (10) and the contents of the nth or (n+1)th memory cell is changed in alternate cycles.

Abstract: The phase of a complex number I+jQ is computed using a hybrid lookup table and computation approach suitable for DSP implementation and useful in remote access/networking and wireless applications. An approximate phase &thgr;˜ for an approximation complex number I˜+jQ˜ is determined through memory table lookup. This is added to a correction phase &Dgr;&thgr; which is determined by calculation of a correction term C=(I˜*Q−Q˜*I)/(I*I˜+Q*Q˜) which represents the imaginary part divided by the real part of the complex multiplication of the complex number and the conjugate of the approximate complex number.

Abstract: A programmable, reconfigurable Reed-Solomon encoder/decoder allows for flexible reprogramming of encoders and decoders for a variety of applications. The standard Reed-Solomon parameters of the Galois Field order, the primitive polynomial, the number of symbols for each codeword of the transmitted and source data are settable via writable registers. The Reed-Solomon encoder/decoder may be coupled to a digital signal processor which specifies the parameters loaded in the writable registers via data register space of data memory space. The decoder and encoder parameters are separately specified and the decoder and encoder can run simultaneously and independently.

Abstract: A monitoring apparatus (10) includes a video camera (12) with a section (16) that permits remote control of the camera. A computer 24 subjects video images from the camera to video processing (61-63), which includes temporal sampling, spatial sampling, and dithering. The processed image (71) is integrated into a document in hypertext mark-up language format. A portable unit (46) is operatively coupled to the computer through a wireless link (49), a cellular base station (36), and a network (38) or telephone line (41). An infrared sensor (19) can detect an event of interest in the monitored area, causing the computer to place a telephone call to the portable unit. The person possessing the portable unit can then use the portable unit to access the document which contains the processed image through the network, in order to observe or verify the event. The person can also use the portable unit to remotely control the operation of the video camera.

Abstract: A differential voltage sense circuit has a fuse placed in one upper leg of a resistance bridge while the remaining upper leg (sense leg) employs a resistor constructed of doped poly or poly silicide or constructed of the doped silicon that forms the N-well or P-well in CMOS process. The lower legs each have a switch selected from a pair of matched switches. A comparator, latch and combinational logic sense the state of the fuse in the resistance bridge and latch the state information before the switches can operate to stop the flow of current in the resistance bridge. The differential voltage sense circuit can operate at low voltage levels compatible with advanced CMOS processes.

Abstract: An architecture and method of fabrication for an integrated circuit 200 having a bond pad 208; at least one portion of said integrated circuit disposed under said contact pad and electrically connected to said pad through a via 205; a combination of a bondable metal layer 207, a stress-absorbing metal layer 203, and a mechanically strengthened, electrically insulating layer 204; and said combination of layers separating said contact pad and said portion of said integrated circuit, and having sufficient thickness to protect said circuit from bonding impact.

Abstract: A circuit for power-off state storage in an electronic device having a positive power supply includes a storage circuit comprising first and second storage capacitors and a write circuit having a plurality of N-type transistors coupled to the storage circuit. The write circuit is operable to write a data bit to the first and second storage capacitors. The power-off state storage circuit also has a sense amplifier connected to the storage circuit and that is operable to read the data bit stored by the storage capacitors. The first and second capacitors in the storage circuit are electrically isolated from the positive power supply such that when the positive power supply is terminated any charge stored on the first and second capacitors is prevented from discharging to the terminated power supply.

Abstract: A non-contact post CMP clean-up process. A corrosion inhibitor is used to protect the copper (118) surface to prevent an electrochemical reaction between the p-well and n-well areas. A multi-step wet chemistry is used to clean all exposed surfaces without etching more than 100 Å of the dielectric (110), copper (118), or liner (116). The first step uses a basic solution and a surfactant (124). The second step uses a diluted HF solution (126) and the third step uses an organic acid solution (128).

Abstract: A synchronous semiconductor memory device in a test mode of operation receives an external clock signal and is controlled by an internal clock adjustment circuit producing an internal clock signal of high frequency to provide write and read operations. A clock cycle converter circuit included in the internal clock adjustment circuit included in the internal clock adjustment circuit produces the internal clock signal by performing a hierarchical exclusive-OR operation on a specific pair of two of eight clock signals successively delayed in phase with respect to the external clock signal.

Abstract: A multi-channel adaptive filter system for use, for example, in echo cancellation for generating an echo estimate for each channel is described. The system includes a forward and backward prediction filter parameter generator that in response to the multi-channel inputs generates a single forward prediction filter vector signal {right arrow over (&ohgr;)}p−1(n) and corresponding single forward error F(n) signal and a single backward prediction filter vector signal {right arrow over (&ngr;)}p−1(n) and corresponding single backward error signal B(n). The system further includes an error generator responsive to errors in the estimated signal for multiplying the errors by a 1-&mgr; where &mgr; is a constant for generating error vector signals {right arrow over (e)}i.p-{right arrow over (e)}J,p(n) for each channel.

Abstract: A method and system for policing Asynchronous Transfer Mode (ATM) traffic, or for performing traffic shaping under ATM protocol, are disclosed. The disclosed system may be implemented into an ATM hub (22), ATM switches (24, 28), or in network routers (30), at which either a User-to-Network or Node-to-Network interface is present. Parameter memory (38) in scheduling circuitry (34) of these devices stores a difference field value (TAT-L)*, limit field value L*, and increment field value I for each virtual channel being handled. The difference field value (TAT-L)* is stored using fewer bits than used by a global timer (54) to monitor global time and represent arrival time of cells, and both the difference field value (TAT-L)* and the limit field value L* are stored as two's complements of their actual value.

Abstract: An Asynchronous Transfer Mode (ATM) switch (8) and method of operating the same to allocate Available Bit Rate (ABR) communications therethrough is disclosed. The switch (8) receives resource management (RM) cells over a sequence of measurement periods. Within each measurement period, the message flow associated with a received RM cell is identified, and a flag (SEEN1) in a memory array (22) is interrogated to determine whether an RM cell for the message flow has yet been received in the measurement period. If not, a sum value (SUM) is updated with the current cell rate (CCR) of the flow and, if the CCR of the flow is equal to or greater than the highest cell rate (r1) yet measured in the measurement period, a highest cell rate field (r1) in memory and a count (m1) of flows having the highest cell rate are updated.

Abstract: A method for improving the accuracy, from ±2.5% to less than ±1%, and time, from 8 seconds to less than 4 seconds, for trimming the dual frequency of an integrated circuit oscillator while reducing the effects of transistor mismatch and power supply variations. This method picks trim values for the two frequencies using a combination of binary and linear searching techniques, and then performs tests to assure that the trimmed oscillator frequencies are well within specification. To save circuitry, the coarse adjust binary value (typically 4 bits) is shared between the two frequencies with only the fine adjust binary values (typically 3 bits) requiring separate values. This method compensates for the fact that the desired ratio between the two frequencies is not constant, but decreases as the coarse trim setting increases, and provides an optimal trim of the two desired oscillator frequencies by setting on-chip fuses.

Abstract: A method to form an embedded FLASH integrated circuit with reduced processing steps is described. In the method a partial etch is performed on the control gate region of a polycrystalline silicon film (21). A multiple etch process is then used to simultaneously form the FLASH memory cell gate stack (54), the NMOS gate structure (94) and the PMOS gate structure (96).

Abstract: The stress at the edges of a thin film conductor can be reduced by noncoincident layered structures, which takes advantage of the characteristic stress polarity changing from tensile to compressive or vice versa in the edge vicinity in order to avoid device reliability and performance problems. By using noncoincident layered structures, destructive stress interference from different layers can be achieved to reduce the stress or stress gradient at the edge. The structures and methods disclosed herein can advantageously be used in many integrated circuit and device manufacturing applications (including gates, wordlines, and bitlines).

Abstract: Utterance-based mean removal in log-domain, or in any linear transformation of log-domain, e.g., cepstral domain, is known to improve substantially a recognizer's robustness to transducer difference, channel distortion, and speaker variation. Applicants teach a sequential determination of utterance log-spectral mean by a generalized maximum a posteriori estimation. The solution is generalized to a weighted sum of the prior mean and the mean estimated from available frames where the weights are a function of the number of available frames.

Abstract: A memory cell array (300) is disclosed having variable pitch word lines and bit lines. The word lines include central word lines (302a) having a first pitch, and peripheral word lines (302b), situated proximate to the edge of the array (300), having a second pitch that is greater than the first pitch. In a similar fashion, the bit lines include central bit lines (304a) having a third pitch, and peripheral bit lines (304b), situated proximate to the edge of the array (300), having a fourth pitch that is greater than the third pitch. The increase in word line and bit line pitch can reduce the adverse results of proximity effects caused by the junction of the dense array features with the relatively open features of the adjacent periphery circuits.