Abstract: This invention has enabled a new, simple thin film nanoporous dielectric fabrication method. In general, this invention uses glycerol, or another low volatility compound, as a solvent. This new method allows thin film aerogels/low density xerogels to be made without supercritical drying, freeze drying, or a surface modification step before drying. Thus, this invention allows production of nanoporous dielectrics at room temperature and atmospheric pressure, without a separate surface modification step. Although this new method allows fabrication of aerogels without substantial pore collapse during drying, there may be some permanent shrinkage during aging and/or drying. This invention allows controlled porosity thin film nanoporous aerogels to be deposited, gelled, aged, and dried without atmospheric controls.

Abstract: A method and system for providing optimal tuning for complex simulators. The method and system include initially building at least one RSM model having input and output terminals. Then there is provided a simulation-free optimization function by constructing an objective function from the outputs at the output terminals of the at least one RSM model and experimental data. The objective function is optimized in an optimizer and the optimized objective function is fed to the input terminal of the RSM. Building of at least one RSM model includes establishing a range for the simulation, running a simulation experiment for the designed experiment, extracting relevant data from said experiment and building the RSM model from the extracted relevant data. The step of running a simulation experiment comprises the step of running a DOE/Opt operation.

Abstract: A method for obtaining a reliable estimate of the transmitter clipping error compliant with T1.413 ADSL standard is disclosed. An architecture is disclosed that uses the clipping error estimate at the receiver to reconstruct a frequency-domain compensation signal. The method for computing the compensation signal is disclosed along with an asymmetric digital subscriber line modem supporting T1.413 standard transmission/reception functions over a discrete multi-tone communications system capable of estimating clipping errors and computing clipping compensation signals.

Abstract: The purpose of this invention is to provide a type of conductor wires which are appropriate for making a thin semiconductor device and can minimize problems of short-circuits between wires. This invention pertains to a type of conductor wires for electrically connecting a semiconductor chip to external conductors. According to this invention, each of conductor wires (5) has first end portion (5a) bonded to electrode pad (2) of semiconductor chip (1), second end portion (5b) bonded to external conductor (4), and bending point (A1) which is positioned between the aforementioned first and second end portions and is bent almost in the direction opposite to the direction that the conductor wire rises at the aforementioned first end portion.

Abstract: A method for validating flash memory includes selecting for execution and executing, from a plurality of setup procedures available for the memory, a memory validation setup procedure setting respective values for a plurality of parameters that are also parameters set by execution of the other of the plurality of setup procedures. The method also includes determining that validation of a particular sector of the flash memory is desired and validating the particular sector of the flash memory, including examining the values of the plurality of parameters.

Abstract: A semiconductor memory device (300) having a parallel test circuit is disclosed. A test data path (308) receives parallel I/O line (I/O0-I/O7) values, and generates therefrom test result data values (PASS and DATA_TST). The test result data values (PASS and DATA_TST) are coupled to a gate control circuit (312). The gate control circuit (312) provides either a first logic value, a second logic value, or an intermediate logic value to an open drain output driver (314) depending upon the test result data values (PASS and DATA_TST). In response to the logic values received from the gate control circuit (312), the open drain output driver (314) drives a data output (DQ) to a first, second or intermediate logic level.

Abstract: A clock multiplier (40) comprises a digital phase lock loop circuit having a single variable delay stage (44) for generating high and low phases for the output clocks. The variable delay stage (44) includes a commutator 64 which chooses between the signal propagating on first and second delay paths (52 and 54). The delay on the delay paths can be incrementally adjusted using capacitors (58 and 61) selectively enabled between the path and ground. If the variable delay is insufficient to lock the output to the reference clock, a prescaler (72) automatically divides the output as needed. A stutter mode prevents short pulses, caused by a transition of the reference clock arriving shortly after the transition of the output clock to a low state, from being passed to the clock multiplying circuitry. The clock multiplier (40) may use a free running mode after lock is obtained, where adjustments are made relative to the degree of difference between the output clock and the reference clock.

Abstract: A clock generation circuit 122 with a selectable non-overlap time period is described for use on an integrated circuit. A master clock signal M which has a latching edge is formed in response to a reference clock signal fclk. A slave clock signal S which has a driving edge is also formed in response to the reference clock signal. The driving edge of slave clock S is delayed by a non-overlap feedback path 504 so that the driving edge is delayed by the non-overlap time period after the latching edge of master clock M. The value of the non-overlap time period is selected by switching delay circuitry 531 in or out of the non-overlap feedback path on signal line 504. A control signal STRSTST is set high or low to select the value of the non-overlap time period. A sense circuit 561 or a scan latch 562 also can select the non-overlap time period.

Abstract: An automatic recovery method for a Die Bonder Wafer Table in the event of loss of wafermap coordinate data is provided. If after moving to the first map die position and there is no die, the wafer table is moved back one die position in the direction of the track from the reference die to the first map die and then the closest coordinate from the map data of current bin in reverse direction is found and the table is moved to that position. If there is alignment fail or no die, the same step of moving back and finding the closest die coordinate from the map data in reverse direction and moving to that position is repeated. Otherwise, the next die coordinate from the map data of the current bin in reverse direction towards the first map die is found and the table is moved to this die coordinate position. The table is moved to the next die position in the forward direction if alignment fails or no die is encountered.

Abstract: A modified flow for ASIC place an route software flow which allows incorporation into the flow, a process for tracking the locations of substrate contacts and well-ties within and outside the boundaries of placed cells and generating required supplemental placements, making possible an efficient use of silicon chip area expended in the adequate placement of substrate contacts and well-ties.

Abstract: The objective of the invention is to make the n-type silicon region, that relatively strongly and adversely affects the dependence of titanium silicide resistance on wire thickness, as small as possible, in common gate electrode wiring with a CMOS structure. The region, into which ions of n-type impurity 6 are implanted, is only the element region of a p-type substrate region, and all the rest of the gate electrode wiring, on the n-type substrate region and field region, is constituted by p-type polysilicon, with relatively good low-resistance titanium silicide formation.

Abstract: A circuit for providing commutation control signals to a commutator for a polyphase brushless dc motor in a mass data storage device includes an accumulator (48) to accumulate a digital count that is proportional or related to a phase difference between the commutation control signals and a motor bemf. A digital variable frequency oscillator (52) generates an oscillator output signal of frequency proportional to the digital count to reset the accumulator (68) after a predetermined time determined by the frequency. The circuit may also include a digital filter (50) between the digital accumulator (48) and the digital variable frequency oscillator (52) to generate a magnitude signal (DRC) of magnitude proportional to the accumulated count for delivery to the variable frequency oscillator (52) to control the frequency thereof.

Abstract: This invention is a testing technique for an electronic circuit such as an integrated circuit. The electronic circuit includes a JTAG test access port and at least one testable embedded core circuit having its own JTAG compliant second test access port. A test access port controller and a programmable switch control testing of the electronic circuit. An internal state in the test access port controller, such as bits in a data register, controls the switch state of the programmable switch. When an embedded core circuit is connected for test, the test access port controller remains responsive to the first test access port and operates in a set of snoopy states corresponding to the state of the embedded core circuit under test.

Abstract: A capacitor (110) having a bottom plate (104) that comprises undoped polysilicon (106) which has been silicided (108). An advantage of the invention is providing a capacitor (110) having reduced parasitic capacitance to the substrate (100) and reduced sheet resistance of the bottom plate (104).

Abstract: A Micro Electro-Mechanical System (MEMS) switch (100) having a bottom electrode (116) formed over a substrate (112) and a thin protective cap layer (130) disposed over the bottom electrode (116). A dielectric material (118) is disposed over the protective cap layer (130) and a pull-down electrode (122) is formed over the spacer (120) and the dielectric material (118). The protective cap layer (130) prevents the oxidation of the bottom electrode (116). The thin protective cap layer (130) comprises a metal having an associated oxide with a high dielectric constant. A portion (132) of the thin protective cap layer (130) may oxidize during the formation of the dielectric material (118), increasing the capacitance of the dielectric stack (128).

Abstract: An enhanced antenna apparatus suitable for use with portable wireless devices. The antenna of the present invention comprises a conductive sleeve having an inner core that can accommodate one or more signal wires passing therethrough. The conductive sleeve functions as the radiating element of the antenna. The length of the conductive sleeve is made an integer multiple of one half the wavelength of the desired frequency. By passing the signal wires through the conductive sleeve the mutual impedance between the antenna itself and signal wires passing through the antenna is eliminated. Alternatively, the antenna can be constructed on a printed circuit board using elongated printed pattern on the top and bottom layers of the printed circuit board. The length of the printed pattern is made an integer multiple of one half wavelength of the desired frequency.

Abstract: Varying the porosity through the thickness of a porous silicon layer allows conflicting needs to be met by the same layer: a low porosity surface layer allows a high-quality epitaxial layer of silicon to be grown, or can provide structural support, while greater porosity in other portions of the layer increases circuit isolation and provides stress relief between layers.

Abstract: Data transfers involving accesses of multiple banks of a DRAM having a shared sense amplifier architecture can be performed while also avoiding bank conflicts and associated data bus latency. Groups of DRAM banks which can be sequentially accessed during a given data transfer without conflicting with one another are identified and utilized for data transfers. Each data transfer sequentially accesses the banks of one of the groups. The sequence in which the banks of a given group will be accessed during a data transfer can advantageously be reordered in order to prevent conflicts with banks that have been or will be accessed during prior or subsequent data transfers. In this manner, consecutive data transfers, each involving accesses to multiple banks of a DRAM having a shared sense amplifier architecture, can be performed without any data bus latency between or within the transfers.

Abstract: An epitaxial layer of silicon is grown on a layer of partially-oxidized porous silicon, then covered by a capping layer which provides structural support and prevents oxidation of the epitaxial layer. A high-temperature anneal allows the partially oxidized silicon layer to separate into distinct layers of silicon and SiO2, producing a buried oxide layer. This method provides a low cost means of producing silicon-on-insulator (SOI) wafers.

Abstract: A silicide process using a pre-anneal amorphization implant prior to silicide anneal. A layer of titanium is deposited and reacted to form titanium silicide (32) and titanium nitride. The titanium nitride is removed and a pre-anneal amorphization implant is performed to enable increased transformation of the silicide (32) from a higher resistivity phase to a lower resistivity phase. A heavy dopant species (40) is used for the pre-anneal amorphization implant such as arsenic, antimony, or germanium. After the implant, the silicide anneal is performed to accomplish the transformation. An advantage of the invention is providing a silicide process having reduced silicide sheet resistance for narrow polysilicon lines.