Abstract: A pipelined analog-to-digital converter system (10) is responsive to an analog input signal (18). The system includes four pipeline stages (11-14), which each produce a respective digital output (26-29) that is coupled to a combining circuit (16). The combining circuit generates the digital output (41) of the system. Each pipeline stage includes an analog-to-digital converter (101), which generates the digital output for that stage. A shuffler circuit (103) randomly shuffles the bits of this digital output, in order to generate shuffled switching signals, which in turn are used to control electronic switches (206-209, 211-214) associated with several capacitors (C1-C4). By randomly shuffling the switching signals, the effects caused by variation of any capacitor from an ideal value are randomized. This avoids nonlinearity such as harmonic distortion in the analog output signal (21) from that stage.

Abstract: A radio frequency receiver includes a mixer (508) for converting a radio frequency signal into an IF signal. The IF signal is then filtered and amplified by a filter (510) and automatic gain control circuit (512). The filtered and amplified IF signal is then received by an analog-to-digital converter (514) in order to convert the signal from an analog signal into a digital signal. The digital signal is then provided to a decimation filter (516) in order to convert the digital signal into a base band signal (520). The ADC (514) and decimation filter (516) both are provided with a sampling frequency signal (518) which is preferably at least four times greater than the IF signal. By using a decimation filter (516) the need for a second down conversion mixer is eliminated, thereby eliminating any associated noise, power consumption and distortion associated with using a second mixer.

Abstract: An EEPROM cell (10) formed on a substrate (18) using conventional process steps is provided. The cell (10) includes first (12) and second (14) conductive regions in the substrate (18) below the substrate's outer surface (28), and the first (12) and second (14) conductive regions are laterally displaced from one another by a predetermined distance (32). The cell (10) also includes an insulating layer (20) outwardly from the outer surface (28) of the substrate (18) positioned so that its edges are substantially in alignment between the first (12) and second (14) conductive regions. The cell (10) further includes a floating gate layer (22) outwardly from the insulating layer (20) and in substantially the same shape as the insulating layer (20). The cell (10) also includes a diffusion region (24 or 26) that extends laterally from at least one of the first (12) and second (14) conductive regions so as to overlap with the insulating layer (20).

Abstract: An integrated circuit (10) is disclosed comprising a fundamental frequency oscillator comprising a reference node (32) whose voltage varies between a high threshold and a low threshold. The fundamental frequency oscillator is operable to generate a first output at the fundamental frequency on a first output node (36). The integrated circuit (10) also comprises a circuit (C2) coupled to the reference node. The circuit (C2) is operable to sense the voltage at the reference node (32), to determine when the voltage exceeds an intermediate threshold between the high threshold and the low threshold, and to generate a second output in response to the determination. The integrated circuit (10) also comprises logic (40) coupled to the circuit (C2) and load circuitry (50) coupled to the logic (40). The logic (40) is operable to generate an output signal at an output frequency greater than the fundamental frequency in response to the second output and the first output.

Abstract: A method for determining the center (62) of a silicon wafer (54) on a wafer table (14) is provided. The method includes measuring silicon wafer data with a sensor (22). The silicon wafer data is received at a wafer center computing system (38). The coordinates of the wafer center (Xw,Yw) in a wafer table Cartesian coordinate system (72) are computed. The coordinates of the edge of the silicon wafer (54) are then determined from the wafer center coordinates (Xw,Yw).

Abstract: The present invention is a channel-aided, decision-directed delay-locked loop (CADD-DLL) implemented, in one embodiment of the present invention, for pilot-symbol-aided (PSA) code-division multiple-access (CDMA) communication. In one embodiment of the present invention initial pseudo-noise (PN) code acquisition is accomplished with the aid of a conventional non-coherent PN code acquisition system, and, upon acquiring the initial PN code epoch, PN code tracking is performed using a channel-aided, decision-directed PN code tracking mechanism. The tracking loop in accordance with the present invention includes delay and advance PN correlators. The correlators are followed by data and phase correction as well as amplitude matching devices, the outputs of which are subtracted to form an error signal for code tracking purposes.

Abstract: The stress at the edges of a thin film conductor can be reduced by noncoincident layered structures, which takes advantage of the characteristic stress polarity changing from tensile to compressive or vice versa in the edge vicinity in order to avoid device reliability and performance problems. By using noncoincident layered structures, destructive stress interference from different layers can be achieved to reduce the stress or stress gradient at the edge. The structures and methods disclosed herein can advantageously be used in many integrated circuit and device manufacturing applications (including gates, wordlines, and bitlines).

Abstract: A method is disclosed for controlling the voltage applied to a voice coil motor coil during the retract operations of a mass storage device, comprising a combination of three different voltage regulator stages. This method includes providing a first circuitry stage adapted to source current to a voice coil motor apparatus, raising the voltage across the voice coil motor to a desired level, providing a second circuitry stage adapted to draw current from the voice coil motor effecting a desired voltage across the voice coil motor, and providing a third circuitry stage adapted to raise the voltage of the voice coil motor to ground by effectively shorting the voice coil motor to ground.

Abstract: A method and apparatus for controlling a lamp. A timer (106) reads a rated safe life value from a memory (102) associated with a lamp in a lamp module (104). The memory (102) in the lamp module (104) contains a series of locations in which the rated safe life of the lamp has been stored, and a series of locations for storing the elapsed on time of the lamp. The timer controller (106) reads the series of locations storing the rated safe life of the lamp and verifies the validity of the values using a series of checksums and comparisons between the various values. The timer controller (106) also reads the series of locations storing the elapsed on time for the lamp and verifies the elapsed on time in a similar manner. If either the rated safe on time or the elapsed on time cannot be verified, the lamp is disabled. If both can be verified, and the lamp is enabled until the elapsed on time equals or exceeds the rated safe life.

Abstract: A method for N-best search for continuous speech recognition with limited storage space includes the steps of Viterbi pruning word level (same word, different time alignment, thus non-output differentiation) states and keeping the N-best sub-optimal paths for sentence level (output differentiation) states.

Abstract: A content addressable memory (CAM) system (50) is disclosed which includes a CAM array (52) for storing an array of data words. More than one data word is stored on each row with the bits of the data word columns interleaved with each other. The CAM array (52) is accessed during one of several modes of operation in accordance with signals from a bit line controller (54) which activate certain ones of a plurality of bit lines coupling the bit line controller (54) to the CAM array (52). The modes of operation, as indicated by a mode control signal, include a write mode, a read mode and a match mode. In first embodiment of the present invention, the bit line controller (54) sequentially accesses each of the columns of data words by selectively activating certain of the bit lines in accordance with a column address signal and the mode control signal.

Abstract: A memory management method is described for reducing the size of memory required in speech recognition searching. The searching involves parsing the input speech and building a dynamically changing search tree. The basic unit of the search network is a slot. The present invention describes ways of reducing the size of the slot and therefore the size of the required memory. The slot size is reduced by removing the time index, by the model_index and state_index being packed and by a coding for last_time field where one bit represents a slot is available for reuse and a second bit is for backtrace update.

Abstract: A thick copper interconnection structure and method for an LDMOS transistor for power semiconductor devices. A large LDMOS transistor is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain. Gate regions are formed between the alternating source and drain diffusions. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form a source and a drain bus. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive copper layer.

Abstract: According to the invention, a method and an amplifier e.g. of the class D type, in particular connected as class BD, wherein an audio signal is pulse-with modulated in that two sets of switches are adapted to make and break signal paths transferring pulses representing the non-inverted or inverted part of the audio signal, comprise attenuating noise and zero crossing distortion which occur because of crosstalk between modulator and control circuit halves in the amplifier. Noise and zero crossing distortion are attenuated by delaying the pulses which represent the non-inverted part and the inverted part, respectively, of the audio signal relative to each other, when the audio signal is in the vicinity of the value 0, thereby achieving modulation of the audio signal which contains characteristics from pulse with modulation of both class AD and BD type.

Abstract: The objective of this invention is to reduce the layout area while guaranteeing data retention stability in a static type semiconductor memory cell. This SRAM cell is constituted with two MOS transistors 10 and 12 and one inverter circuit 14. The source terminal of PMOS transistor 10 is connected to bit line (BL), the drain terminal is connected to data storage node (Na), and the gate terminal is connected to word line (WL). The source tenninal of NMOS transistor 12 is connected to a supply voltage terminal that provides low-level reference potential VSS (for example, zero volts), the drain terminal is connected to data storage node (Na), and the gate terminal is connected to the output terminal o inverter circuit 14. The input terminal of inverter circuit 14 is connected to data storage node (Na).

Abstract: In one embodiment of a horizontal bipolar transistor constructed in accordance with the teachings of this invention, oxygen is implanted into the horizontal bipolar transistor to provide a silicon dioxide layer between the base and the collector and emitter of the horizontal bipolar transistor. This silicon dioxide layer reduces the actual interface area of the base to collector and base to emitter junctions, thereby decreasing the capacitance of the transistor. In addition, the dielectric constant of the silicon dioxide layer is such that the capacitance across the silicon dioxide layer, and thus between the base and the collector and emitter, is minimal relative to the base to collector and base to emitter capacitance provided by the base to collector and base to emitter junctions themselves. In an alternative embodiment, nitrogen ions are implanted to form silicon nitride regions rather than silicon dioxide regions.

Abstract: The improved rinse tank includes an external shell and an internal shell. For one embodiment, the external shell preferably defines a five sided open-top tank with a top open to the atmosphere. The internal shell is preferably disposed within the external shell and has a configuration that will accommodate at least two semiconductor wafer boats filled with six inch semiconductor wafers. The external shell is preferably sized large enough to completely immerse the wafer boat and wafers in water when the rinse tank is filled. A chamber may be formed between the external shell and the internal shell within the lower portion of the rinse tank. Two or more deionized water inlets may be provided at the bottom of the rinse tank at opposite corners. Three or more compressed air nozzles may also be provided at the lower portion of the rinse tank. Multiple deionized water jet ports are provided at the internal shell.

Abstract: An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate, the method comprising the steps of: forming a conductive structure insulatively disposed over the semiconductor substrate (step 302 of FIG. 3); introducing a silicide enhancing substance into the conductive structure (step 304 of FIG. 3); amorphizing a portion of the conductive structure; forming a metal layer on the conductive structure (step 310 of FIG. 3); and wherein the metal layer interacts with the silicide enhancing substance in the amorphized portion of the conductive structure so as to form a lower resistivity silicide on the conductive structure. The conductive structure is, preferably, comprised of: doped polysilicon, undoped polysilicon, epitaxial silicon, or any combination thereof. Preferably, the silicide enhancing substance is comprised of: molybdenum, Co, W, Ta, Nb, Ru, Cr, any refractory metal, and any combination thereof.

Abstract: A HDD write driver circuit (30) having two sets of boost devices (Q1, M2, and Q2, M1) which are temporarily turned on during a current reversal to boost the normal current and increase the differential transient voltage across the coil (LS) while decreasing the TRTF. During a current reversal cycle, one set of transistors is turned on while the other set is left off. The on set to pulls the node at one end of the coil substantially to the positive rail, and pulls the other node at the other end of the coil substantially to the lower rail (Vee). The boost FETs (M1, M2) are preferably large PMOS devices that must be driven hard to achieve a quick transient switching time. Advantageously, when one of the PMOS FETs (M1, M2) are on, the associated series resistor (RS) is bypassed.

Abstract: A circuit (41) to provide drive voltages to a voice coil motor (VCM) (50) of a hard disk drive (10) has identical high and low side drivers (42, 44, 46, and 48) connected to the VCM (50). Each driver has an output FET (52) selectively connecting the VCM (50) to a control voltage (58). A Class-AB output pair (54 and 54′) in parallel with the output FETs (52 and 52′) provides continuous and linear Class-AB operation at the output node (60) around the crossover point, while the output FETs (52 and 52′) are kept not conducting. This approach offers extremely low level of crossover harmonic distortion. Each FET of the Class-AB pair (54 and 54′) is connected to a biasing FET (56 and 56′) to provide the desired Class-AB quiescent current. Preferably the output FET (52), quiescent current controlling FET (54), and biasing FET (56) are fully integrated.