Abstract: A circuit for improving the performance of a charging capacitor inverter used in VCO and similar circuits. The disclosed approach is used to provide both trip point and charging current delay control to reduce the amount of “jitter” associated with the circuit. Trip point delay control is accomplished by adding an in-line transistor, output in a typical charged capacitor inverter, between the charging capacitor and the circuit. The threshold of this transistor is controlled by a dc bias level (control voltage) which allows this transistor to turn “ON” or “OFF” when the node voltage of the capacitor reaches the controllable preset level. Further control of the circuit's delay is obtained by means of circuitry which allows the amount of capacitor charging current to be selected.

Abstract: A general purpose microprocessor architecture enabling more efficient computations of a type in which Boolean operations and arithmetic operations conditioned on the results of the Boolean operations are interleaved. The microprocessor is provided with a plurality of general purpose registers (“GPRs” 102)and an arithmetic logic unit (“ALU” 104), capable of performing arithmetic operations and Boolean operations. The ALU has a first input (108) and a second input (110), and an output (112), the first and second inputs receiving values stored in the GPRs. The output stores the results of the arithmetic logic unit operations in the GPRs. At least one of the GPRs is capable of receiving directly from the ALU a result of a Boolean operation. In one embodiment, at least one of the GPRs (PN)capable of receiving directly from the ALU a result of a Boolean operation is configured so as to cause the conditioning of an arithmetic operation of the ALU based on the value stored in the GPR.

Abstract: This invention is to a method for producing a uniform nitrogen doped layer in silicon that effectively reduces boron transient enhanced diffusion (TED) for ultra shallow junction formation. A silicon substrate (10) from an n-type single crystal silicon grown in the [100] direction and cut into wafers with (100) faces exposed is pre-amorphized by silicon and germanium implantation (11). Nitrogen is implanted to a depth of 0.7 &mgr;m through the amorphous layer with multiple implantations at energies ranging from 10 keV to 250 keV (12). Boron is implanted into the pre-amorphized and nitrogen contained silicon substrate (13). After boron implantation, the substrate is subjected to a rapid thermal anneal process to remove lattice damage and activate boron. The resulting nitrogen and boron profiles (14) in the substrate of this invention exhibit suppressed boron TED and enable formation of p+ ultra shallow junctions.

Abstract: A semiconductor device is disclosed. The device includes an integrated circuit chip having integral de-coupling capacitors on the chip backside. The de-coupling capacitors includes a metal layer in intimate contact with the semiconductor substrate of the integrated circuit, a dielectric layer and a second metal layer. The second metal layer is segmented to form multiple capacitors, and each capacitor is interconnected to power supplies of the chip. Interconnection to different integrated circuit packages is provided. A method of making the semiconductor device is also disclosed.

Abstract: A capacitor electrode and method of making having increased surface area because of the presence of pits in the side walls of the electrode thus increasing the capacitance of the capacitor while still maintaining the packing density of the integrated circuit.

Abstract: A process for the fabrication of an integrated circuit assembly, using thin film platinum metallization to provide edge-side contacts suitable for solder ball connections. Three-dimensional laser ablation may be used for patterning metal films. A multi-chip assembly may be formed using orthogonal edge-side mounting on a substrate.

Abstract: Chemical mechanical polishing slurry with functionalized silica abrasive particles, the functionalization permits high pH slurry without rapid degradation of silica particles and also permits the modification of surface properties of abrasive particles to modify slurry behavior. One example of modified behavior would be to enhance selectivity by controlling particle interaction with different surfaces on the wafer.

Abstract: A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data.

Abstract: A modem (55) including receive circuitry (30) implemented by way of a digital signal processor (32, 32′) is disclosed. The receive circuitry (30) operates according to a receive clock (CLKr) that is based upon the output of a free run oscillator (50). An incoming frequency multiplexed signal (f(t)) is sampled by an analog-to-digital converter (31) and demodulated by way of a Fast Fourier Transform function (36). After such demodulation, a phase rotation function (40) applies a phase shift to the demodulated signal corresponding to an estimated phase offset (&tgr;) between the receive clock (CLKr) and a pilot signal (P) transmitted by the transmitting modem; a finite impulse response filter function (42) applies a digital filter to the demodulated signal to correct for phase error based upon an estimated frequency offset (&Dgr;).

Abstract: A battery charging system is provided which is comprised of a battery pack (30) and a charging system (20). The battery pack (30) includes a battery (10) and a battery capacity detect circuit (32). The battery capacity detect circuit (32) having a memory is interfaced with the charging system (20) through a communication link to output a CHG-Bar signal. The battery capacity detect circuit (32) is operable to perform numerous monitoring operations on the battery by detecting the charge input to the battery and detecting charge taken away from the battery in a discharge operation. This operation is performed independent of the charging operation by the charging system (20). However, the charging operation of the charger (22) can be affected with the CHG-Bar signal.

Abstract: An improved audio-visual circuit is provided that includes a transport packet parsing circuit for receiving a transport data packet stream, a CPU circuit for initializing said integrated circuit and for processing portions of said data packet stream, a ROM circuit for storing data, a RAM circuit for storing data, an audio decoder circuit for decoding audio portions of said data packet stream, a video decoder circuit for decoding video portions of said data packet stream, an NTSC/PAL encoding circuit for encoding video portions of said data packet stream, an OSD coprocessor circuit for processing OSD portions of said data packets, a traffic controller circuit moving portions of said data packet stream between portions of said integrated circuit, an extension bus interface circuit, a P1394 interface circuit, a communication coprocessors circuit, an address bus connected to said circuits, and a data bus connected to said circuits.

Abstract: A pipeline ADC includes an input stage and a first group of subsequent stages, wherein the input stage includes a unity gain amplifier having an input for receiving an analog input signal, an output, and first and second comparators each having a first input coupled to the output of the unity gain amplifier. The first comparator has a second input for receiving a first reference voltage an first output, and the second comparator has a second input for receiving a second reference voltage and an output. The input stage includes a full adder coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and an output producing MSB bit information.

Abstract: A semiconductor device comprising an integrated circuit and an information unit, said unit being electrically separate from said integrated circuit; an integrated antenna electrically connected with said unit; and an electronic data bank integral with said unit. A method of fabricating an information unit into an integrated circuit chip comprising forming an integrated circuit into a semiconductor substrate using a plurality of process steps; concurrently forming an information unit using a selection of said process steps so that said unit becomes integrated into said chip but remains electrically separate from said integrated circuit; concurrently forming an antenna using a selection of said process steps so that said antenna becomes integrated into said chip and electrically connected to said information unit; providing a data bank within said information unit; and encoding electronic data permanently into said data bank.

Abstract: High-bandwidth, analog multiplexer circuits with low signal feed-through and good common mode properties are described. These are BiCMOS circuits with N-MOS control transistors which emphasize low parasitic capacitance through circuit layout techniques and the use of smaller geometry devices where possible. These circuits can be used in both single-ended and differential configurations and address applications having multiplexing ratio requirements ranging from 2-to-1 up to many-to-1.

Abstract: A low noise, low distortion, power efficient DSL/cable line driver has a double Wheatstone impedance bridge network that functions to prevent contamination of DSL signals that are received by and transmitted from the line driver. The line driver employs an external current sensing impedance that can be either purely resistive or complex and that can be selected to accommodate a particular transmission medium. The line driver further employs an internal programmable resistor that can be programmably adjusted to accommodate changes in transmission medium impedance to optimize sidetone rejection.

Abstract: A fast acting polarity detector uses a “very fast” polarity detector in tandem with a “precise” polarity detector to increase the maximum speed achievable from an A/D converter that employs a 1-bit folding front end. The fast polarity detector is a coarse polarity detector that immediately controls the 1-bit folder. The precise polarity detector operates more slowly, but more accurately. When the output of the precise polarity detector becomes available, it overrides the output of the fast polarity detector. This process does not limit the speed of the A/D conversion even though the precise polarity detector is slower to operate since the signal levels are small.

Abstract: A fast voltage differential signaling (LVDS) transceiver (50) having high repeater speeds up to 1.36 GBps, and also meeting the TIA/EIA-644 standard short-to-ground requirements. A mixed voltage-current mode differential driver has a respective control signal (A3) driving each of the drive transistors (Q3). The control signal (A3) is controlled by a transistor (M1) being a function of current through the respective drive transistor (Q3). A current mirror (Q4, Q5, Q6) is used to mirror current conducting through a transistor (Q4) in parallel with the drive transistor (Q3), which mirror current is compared against a current reference (Iref).

Abstract: A high performance data communications system (e.g., modem, transceiver, etc.) that has improved control over power dissipation is disclosed. The data communications system allows its power dissipation to be adaptively controlled so as to provide substantially improved control over the power dissipation of the data communications system than has been conventionally possible. The control over power dissipation can be performed only on transmissions, only on receptions, or on both transmissions and receptions. By suitably controlling the power dissipation, the power dissipation of the data communications system can be substantially reduced at lower power settings, while still supporting the higher power settings.

Abstract: A circuit (43) generates one or more signals to be delayed by a corresponding time intervals. Tapped delay lines (40) are coupled to the signals, each tapped delay line including a plurality of delay elements (42) and having a plurality of exit points (E) through which said signal may propagate. A test circuit (20) determines a delay associated with a delay element in the circuit and selects one of said exit points of each of said tapped delay lines based on said delay.

Abstract: A data converter (20) comprising an input (I0′-I3′) for receiving a digital word and an output (VOUT2) for providing an analog voltage level in response to the digital word. The data converter further comprises a plurality of bit lines (BL0′-BL3′) formed with an alignment in a first dimension and a plurality of word lines (WL0′-WL4′) formed with an alignment in a second dimension different than the first dimension. Further, the data converter comprises a string (12′) comprising a plurality of series connected resistive elements (R0′-R14′). The string comprises a plurality of voltage taps (T0′-T15′), and at least a majority of the plurality of series connected resistive elements are formed with an alignment in the first dimension. The data converter also comprises a plurality of switching transistors (ST0′-ST15′) coupled between the plurality of voltage taps and the output.