Abstract: A TAB device (10) is coupled to a circuit board (12). The TAB device (10) includes a semiconductor die (11) having leads (18) extending therefrom. A material layer (30), typically a polyimide layer, covers the inward portion of the leads (18) to maintain leading position during attachment of the TAB device (10) to the circuit board (12). Prior to attachment, a backside encapsulation region (40) is applied to the backside of the TAB device (10), sealing the backside of the leads (18). The backside encapsulation material is selected to have a coefficient of thermal expansion similar to the coefficient of thermal expansion of the first material layer (18). The backside encapsulation material is selected to have a coefficient of thermal expansion similar to the coefficient of thermal expansion of the first material layer (30), to prevent excessive warpage.

Abstract: A data storage circuit (30) has a data input (12′) for receiving a data voltage (D′) and a node (17′) for receiving an interim voltage in response to the data voltage. The data storage circuit also includes an output enable circuit (32) for providing at least one conditional path coupled to the node and for coupling the interim voltage to the node. The output enable circuit has a transistor (32p) having a first threshold voltage and operable to provide a conductive path along the at least one conditional path. The data storage circuit also includes a data output (19′) for providing an output voltage in response to the interim voltage at the node and a data retention circuit coupled between the node and the data output. The data retention circuit (18′ and 20′) has at least one transistor having a second threshold voltage higher in magnitude than the first threshold voltage.

Abstract: Methods of controlling the illumination source (18) of an SLM-based display system (10). It is assumed that the system (10) displays pixel data formatted into a bit-plane format so that all bits of the same bit-weight can be displayed simultaneously. To provide greyscale, the amplitude of the source (18) may be modulated so that bit-planes having greater bit-weights are displayed with more intense illumination than bit-planes having smaller bit-weights (FIGS. 2 and 3). To avoid visual artifacts, the duty cycle of the bit-plane display times may be shortened relative to the frame period. (FIG. 4A). The latter method can be accompanied by a shortening of the duty time of the illumination on SLM (15). (FIG. 4B). The short duty cycle method may be used together with illumination amplitude modulation, or it may be used with the PWM method of providing greyscale.

Abstract: A digital self calibration scheme for pipelined AD converters. The scheme can correct for capacitor mismatch, capacitor non-linearity, amplifier gain and amplifier non-linearity.

Abstract: An architecture and method of fabrication for an integrated circuit having a reinforced bond pad comprising at least one portion of the integrated circuit disposed under the bond pad; and this at least one circuit portion comprises at least one dielectric layer and a patterned electrically conductive reinforcing structure disposed in this at least one dielectric layer.

Abstract: A data processing system (15) including a synchronous random access memory (30) and a method for accessing the synchronous random access memory are disclosed. A digital processor (20) of the data processing system is coupled to a system clock circuit (65) that produces a system clock signal for controlling operation of the digital processor. Addressable storage cells within the synchronous random access memory are accessed in response to the system clock signal and an address select signal (ADS) to write data into the storage cells or read data out from the storage cells. Initial row and column addresses are latched into a row address buffer (48) and a column address buffer (49). The data are read out from the memory in an order corresponding to a control signal (WT) in synchronization with the system clock signal. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A semiconductor assembly and method of fabrication comprising an integrated circuit chip, an electrically insulating substrate, a multitude of solder balls for interconnecting both parts while spacing them apart by a gap, and a polymeric encapsulant filling the gap. The method of fabrication includes heating and cooling cycles, based on stress modeling, such that all mechanical stress levels in the dielectric layers of the circuit chip and in the solder balls are reduced to levels safe for operating the semiconductor assembly.

Abstract: A mixed signal codec includes: a multiplexer amplifier 24 having an analog output signal; a sigma-delta analog to digital converter 26 having an input coupled to the analog output signal; and a clipping circuit 40 and 42 coupled to the input of the analog to digital converter for clipping the analog output signal.

Abstract: A non-volatile memory cell comprising a metal oxide semiconductor field effect transistor (MOSFET) fabricated to read back a logic level “one” state and programmable by a gate to drain fusing to read back to a logic level “zero” state. The drain is patterned to enhance the formation of a localized hot spot during device lateral NPN transistor snapback for a controlled meltdown of gate oxide and the creation of an ohmic gate to drain path. A metal oxide semiconductor (MOS) integrated circuit typically includes a plurality of memory cells composing a programmable array. The drains of each memory cell are tied together in parallel and connected to a high-level programming voltage, and the sources are tied to ground.

Abstract: Disposable spacers of an organic material or a low-temperature inorganic material provide advantages in the formation of STI trenches and contact holes and additional freedom in line spacing.

Abstract: A logarithmically controlled attenuator circuit includes a resistive attenuator having a single series resistive element connected between an input conductor and an output conductor, and a plurality of parallel resistive elements each having a first terminal connected to the output conductor. A plurality of switching elements controllably couple the parallel resistive elements, respectively, between the output conductor and a first reference voltage conductor. A control circuit produces successive gradually increasing and then leveling off analog control signals on the control terminals of successive switching elements, respectively. A programmable implementation includes a first group of parallel resistive elements (Q1,3,5 . . . ) each having a first terminal connected to the output conductor (12), and a second group of parallel resistive elements (Q2,4,6 . . . ) each having a first terminal connected to the output conductor (12).

Abstract: A system and method for speed-up of the frequency switching time of a circuit, generally a voltage controlled oscillator having an operating frequency controlling input terminal. A first control circuit is coupled to the frequency controlling input terminal for maintaining the operating frequency of the oscillator at its first selected operating frequency. Circuitry is provided which is responsive to a directed change from the first operating frequency of the oscillator to a second different operating frequency of the oscillator to apply a voltage to the input terminal determined by the size of the directed change in the operating frequency and for a predetermined time period. This circuitry includes a switch coupled to the input terminal, a charge pump coupled to the switch and remote from the input terminal and a timer controlling the current output of the charge pump and the switch. The output of the charge pump is a current which is converted to a voltage.

Abstract: A system for applying a rotary force to strips of varying widths. The system includes a plurality of adjacent tracks of progressively greater width, each of the tracks disposed at a height above all tracks of lesser width. A plurality of rotating members are provided, one rotating member extending into one of the tracks and extending to the surface of the associated track. An adjustable drive disc is adjusted to be disposed over a preselected one of the rotating members and is movable toward the rotating members to apply a rotary force to a strip disposed between the rotating member and the disc. Each of the tracks is defined by a pair of spaced apart surfaces with all of the rotating members being on a common rotating shaft.

Abstract: A method for scaling graphics image data. The method operates on data that is in red-green-blue format. Each component is filtered to extract high pass information and then that information is scaled in amplitude. Finally, the amplitude scaled information is recombined with the original components of the image data. The filtering and amplitude scaling sharpen the scaled image, producing a clearer picture.

Abstract: A vertical field effect transistor (700) and fabrication method with buried gates (704) having gate sidewall crystal orientation the same as the substrate surface and a low index substrate crystal orientation without tilt to a higher index direction. The gate (704) may have modulated doping along the channel (706), and the drain (708) may have a lighter doping level than the channel which may be accomplished by an epitaxial overgrowth of the gates (704) to form the channels (706).

Abstract: A method is given for removing excess oxide from active areas after shallow trench isolation, without the use of chemical-mechanical polishing. A nitride mask protects active areas during the etch of isolation trenches. The trenches are filled with oxide, using high density plasma deposition, which simultaneously etches, providing a sloping contour around the isolation trenches. A further layer of nitride is used to provide a cap over the trench which seals to the underlying layer of nitride. The cap layer of nitride receives a patterned etch to remove the cap only over the active areas. This allows a selective etch to remove the excess oxide, which can be followed by a selective etch to remove the nitride layers.

Abstract: The present invention involves a hysteretic comparator (100) for comparing a sample voltage (VOUT) to a reference voltage (VREF). A hysteresis voltage generator providing a voltage VHYST− and a voltage VHYST+. A first differential input stage (505) generates a signal coupled to a summing node (506, 507) determined from a difference between the sample voltage and VREF. A second differential input stage (504) generates a signal coupled to the summing node determined from a positive difference between VHYST− and VHYST+. A third differential input stage (503) generates a signal coupled to the summing node determined from a negative difference between VHYST− and VHYST+. A control device (512, 513, 514) coupled to selectively enable the second and third differential input stages to select among a first mode and second mode.

Abstract: A circuit breaker (10) is shown having a movable electrical contact (36) adapted to move into and out of engagement with a stationary electrical contact (38, 40). A current carrying thermostatic trip member (42) has a portion movable in response to changes in temperature with a motion transfer member (46) transferring the motion to latch/catch mechanism (20, 24, 30, 32). The catch portion (30, 32) comprises a generally U-shaped adjustment element (30) formed of thermostatic material whose legs are fixed to the base (32a) of a catch member (32) which in turn is pivotably mounted in the casing of the circuit breaker. The bight (30c) of the adjustment element is free to move in response to temperature changes relative to the catch member. Overcurrent will cause the thermostatic trip member to transfer motion to the bight of the adjustment element causing the adjustment element and catch member to pivot and release a latch to thereby open the circuit breaker.

Abstract: A data processing device is provided which has multiprocessors that can be configured on a cycle by cycle basis as loosely coupled or tightly coupled. Bit-stream Processing Unit (BPU) 110 executes instructions from ROM 112 and accesses data from RAM 111. Similarly, Arithmetic Unit (AU) 120 executes instructions from ROM 122 and accesses data from RAM 121. Both processor operate in parallel and exchange data by accessing RAM 121. AU 120 can receive an instruction directive from BPU 110 directing it to perform a selected sequence of instructions in a loosely coupled manner. AU 120 can also receive an instruction directive from BPU 110 directing that a portion of AU 120 operationally replace a portion of BPU 110 for the duration of one instruction which allows data to be passed directly between the processors in a tightly coupled manner.

Abstract: An improved integrated circuit including decryption functions employs a method for determining if its environment has been modified, by providing a first VCXO as part of the integrated circuit, providing a second VCXO, adjusting one of the VCXOs in a first preselected manner, determining a first frequency count of the adjusted VCXO during a first preselected time interval using the other VCXO, adjusting the one of the VCXOs in a second preselected manner, determining a second frequency count of the adjusted VCXO during the first preselected time interval using the other VCXO, averaging the first and second frequency count to provide an average frequency count, adjusting the average frequency count in a predetermined manner, and comparing the adjusted average frequency count to a previously stored, determined, or provided average frequency count to determine if the environment of the integrated circuit has been modified.