Patents Assigned to Varian Semiconductor Equipment Associates, Inc.
  • Patent number: 10256132
    Abstract: Provided herein are approaches for processing reticle blanks. In one approach, a reticle processing system includes a support assembly having a plate coupled to a frame, and a carrier assembly coupled to the support assembly. In one approach, the carrier assembly includes a carrier base coupled to the plate, a reticle disposed over the carrier base, and a carrier shield disposed over the reticle, wherein the carrier shield may include a central opening formed therein, allowing for placement and extraction of the reticle. In one approach, when the carrier assembly is placed atop the support assembly, a plurality of pins extend from the plate through corresponding openings in the carrier base, the plurality of pins supporting the carrier assembly so the carrier base, the reticle, and the carrier shield are each independently supported and vertically separated from one another.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: April 9, 2019
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: James Strassner, Charles Carlson, Robert Brent Vopat, Jeffrey Blahnik
  • Patent number: 10229832
    Abstract: A method of patterning a substrate. The method may include: providing a first surface feature and a second surface feature in a staggered configuration within a layer, the layer being disposed on the substrate, and directing first ions in a first exposure to a first side of the first surface feature and a first side of the second surface feature, in a presence of a reactive ambient containing a reactive species, wherein the first exposure etches the first side of the first surface feature and the first side of the second surface feature, wherein after the directing, the first surface feature and the second surface feature merge to form a third surface feature.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: March 12, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Steven R. Sherman, John Hautala, Simon Ruffell
  • Patent number: 10224181
    Abstract: A processing apparatus may include a plasma chamber to house a plasma and having a main body portion comprising an electrical insulator; an extraction plate disposed along an extraction side of the plasma chamber, the extraction plate being electrically conductive and having an extraction aperture; a substrate stage disposed outside of the plasma chamber and adjacent the extraction aperture, the substrate stage being at ground potential; and an RF generator electrically coupled to the extraction plate, the RF generator establishing a positive dc self-bias voltage at the extraction plate with respect to ground potential when the plasma is present in the plasma chamber.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: March 5, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Costel Biloiu, Piotr Lubicki, Tyler Rockwell, Christopher Campbell, Vikram Singh, Kevin M. Daniels, Richard J. Hertel, Peter F. Kurunczi, Alexandre Likhanskii
  • Patent number: 10222202
    Abstract: An apparatus may include a processor and memory unit, including a control routine having a measurement processor to determine, based upon a first set of scatterometry measurements, a first change in a first dimension of a first set of substrate features along a first direction. The first set of substrate features may be elongated along a second direction perpendicular to the first direction. The measurement processor may be to determine, based upon a second set of scatterometry measurements, a second change in dimension of a second set of substrate features along the second direction, wherein the second set of substrate features is elongated along the first direction. The apparatus may include a control processor to generate an error signal when a figure of merit based upon the first change and the second change lies outside a target range.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: March 5, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Morgan D. Evans, Simon Ruffell, Tristan Y. Ma, Kevin Anglin
  • Patent number: 10221476
    Abstract: A system for extending the life of insulating components disposed within a housing, such as an ion implanter, is disclosed. The system includes one or more insulating components, disposed in the housing, which are coated with a diamond like carbon (DLC) coating. The insulating components may be bushings or any insulating component used to electrically isolate two components having different voltage potentials, such as electrodes. This DLC coating retards the deposition of metals, such as those contained in the ion source, on the insulating components. This reduces the likelihood or electrical arcing or other phenomenon that affect the useful life of these insulating component.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: March 5, 2019
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Craig R. Chaney, Neil J. Bassom
  • Patent number: 10217657
    Abstract: An active substrate alignment system for an ion implanter, the system including a platen, a registration device adapted to selectively move a substrate engagement surface disposed adjacent the platen for limiting movement of a substrate disposed on the platen, a camera configured to capture an image of the substrate before the substrate is disposed on the platen, and a controller in communication with the camera and the registration device, the controller configured to command the registration device to move the substrate engagement surface based on the image to limit movement of the substrate in a predetermined manner.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: February 26, 2019
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Aaron P. Webb, Timothy J. Miller, Tammy Jo Pride, Christopher N. Grant, James D. Strassner, Charles T. Carlson
  • Patent number: 10217654
    Abstract: The present disclosure describes a method and apparatus for determining whether components in a semiconductor manufacturing system are authorized for use in that system. By embedding an identification feature in the component, it is possible for a controller to determine whether that component is qualified for use in the system. Upon detection of an unauthorized component, the system may alert the user or, in certain embodiments, stop operating of the system. This identification feature is embedded in a component by using an additive manufacturing process that allows the identification feature to be embedded in the component without subjecting the identification feature to extreme temperatures.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: February 26, 2019
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Craig R. Chaney, Adam M. McLaughlin
  • Patent number: 10217601
    Abstract: An ion source includes an ion source chamber having a longitudinal axis, the ion source chamber operative to define a plasma therein. The ion source also includes a split solenoid assembly comprising a first solenoid and a second solenoid that are mutually disposed along opposite sides of the ion source chamber, where each of the first solenoid and second solenoid comprises a metal member having a long axis parallel to the longitudinal axis of the ion source chamber, and a main coil having a coil axis parallel to the long axis and comprising a plurality of windings that circumscribe the metal member. The main coil defines a coil footprint that is larger than an ion source chamber footprint of the ion source chamber.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: February 26, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventor: James Buff
  • Publication number: 20190058318
    Abstract: Embodiments of the disclosure provide a current protection device with a mutual reactor including a first winding and a second winding. The current protection device is a subcomponent of a previously developed fault current limiter. The current protection device protects the superconductor from potential damage. The current protection device may include a coil electrically connected in series with the first winding or the second winding, an actuator mechanically coupled at an output of the coil, and an electrical interrupter electrically connected to the first and second windings, wherein the actuator is communicatively coupled with the electrical interrupter to actuate a moveable contact of a set of breaker contacts of the electrical interrupter. In some embodiments, the first and second windings are arranged in parallel to one another. In some embodiments, the coil is electrically coupled to an output of the first winding or the second winding.
    Type: Application
    Filed: October 6, 2017
    Publication date: February 21, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Saeed Jazebi, Paul J. Murphy
  • Publication number: 20190056914
    Abstract: A method of patterning a substrate may include providing a blanket photoresist layer on the substrate; performing an ion implantation procedure of an implant species into the blanket photoresist layer, the implant species comprising an enhanced absorption efficiency at a wavelength in the extreme ultraviolet (EUV) range; and subsequent to the performing the ion implantation procedure, performing a patterned exposure to expose the blanket photoresist layer to EUV radiation.
    Type: Application
    Filed: October 18, 2017
    Publication date: February 21, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Tristan Y. Ma, Huixiong Dai, Anthony Renau, John Hautala, Joseph Olson
  • Publication number: 20190051493
    Abstract: An ion implantation system may include an ion source to generate an ion beam, a substrate stage disposed downstream of the ion source; and a deceleration stage including a component to deflect the ion beam, where the deceleration stage is disposed between the ion source and substrate stage. The ion implantation system may further include a hydrogen source to provide hydrogen gas to the deceleration stage, wherein energetic neutrals generated from the ion beam are not scattered to the substrate stage.
    Type: Application
    Filed: October 9, 2018
    Publication date: February 14, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Frank Sinclair, Daniel Tieger, Klaus Becker
  • Patent number: 10204909
    Abstract: Provided herein are approaches for forming a gate oxide layer for a DRAM device, the method including providing a finned substrate having a recess formed therein, and performing an ion implant into a sidewall surface of the recess to form a gate oxide layer having a non-uniform thickness, wherein a thickness of the gate oxide layer at a top section of the sidewall surface is greater than a thickness of the gate oxide layer at a bottom section of the sidewall surface. In some approaches, the ion implant is provided as a series of ion implants at multiple different implant angles, varied along with an ion implantation energy and/or an ion dose to increase the thickness of the gate oxide of the top section of the sidewall surface. In some approaches, the finned substrate is also exposed to a plasma, either during or after, the ion implantation.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: February 12, 2019
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, Arvind Kumar, Tristan Ma, Kyu-Ha Shim, John Hautala, Steven Sherman
  • Patent number: 10199257
    Abstract: Embodiments of the disclosure include a fixed position mask for workpiece edge treatment. In some embodiments, an apparatus includes a roplat having a rotatable assembly, and a platen coupled to the rotatable assembly, wherein the platen is configured to hold a workpiece. The apparatus further includes a bracket affixed to the rotatable assembly, and a mask directly coupled to the bracket, wherein the mask is positioned adjacent the workpiece. The mask covers an inner portion of the platen and the workpiece, leaving just an outer circumferential edge of the workpiece exposed to an ion treatment. In some embodiments, the platen is permitted to rotate relative to the bracket during an ion treatment. In some embodiments, the mask includes a solid plate section devoid of any openings, and a mounting portion extending from the plate section, wherein the mounting portion is directly coupled to an extension arm of the bracket.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: February 5, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Fletcher Ian Potter, Philip Layne, Keith A. Fernlund, Michael Swears, Richard Allen Sprenkle
  • Publication number: 20190035518
    Abstract: An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer. The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region.
    Type: Application
    Filed: February 27, 2018
    Publication date: January 31, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan
  • Patent number: 10193066
    Abstract: A method may include generating a plasma in a plasma chamber, the plasma comprising an etchant species and extracting a pulsed ion beam from the plasma chamber and directing the pulsed ion beam to a substrate, where the pulsed ion beam comprises an ON portion and an OFF portion. During the OFF portion the substrate may not be biased with respect to the plasma chamber, and the duration of the OFF portion may be less than a transit time of the etchant species from the plasma chamber to the substrate.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: January 29, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Glen F. R. Gilchrist, Raees Pervaiz, Kenneth Starks, Shurong Liang, Tyler Rockwell
  • Patent number: 10192727
    Abstract: An electrodynamic mass analysis system which has the capability of filtering unwanted species from an extracted ion beam without the use of a mass analyzer magnet is disclosed. The electrodynamic mass analysis system includes an ion source and an electrode disposed outside the ion source. The ion source and the electrode are biased relative to one another so as to emit pulses of ions. Each of these pulses enters a tube where each ion travels at a speed related to its mass. Thus, ions of the same mass travel in clusters through the tube. Ions reach the distal end of the tube separated temporally and spatially from one another based on their mass. The ions then enter a deflector, which is energized so as to allow the cluster of ions having the desired mass to pass through a resolving aperture disposed at the exit of the deflector.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: January 29, 2019
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Frank Sinclair, Joseph C. Olson, Costel Biloiu, Alexandre Likhanskii, Peter F. Kurunczi
  • Publication number: 20190027396
    Abstract: A method may include providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising an insulator layer and a silicon layer. The silicon layer may be disposed on the insulator layer, where the silicon layer comprises a first silicon thickness variation. The method may include forming an oxide layer on the silicon layer, where the oxide layer has a uniform thickness. The method may include selectively etching the oxide layer on the silicon layer, wherein the oxide layer comprises a first non-uniform oxide thickness. After thermal processing of the SOI substrate in an oxygen ambient, the non-uniform oxide thickness may be configured to generate a second silicon thickness variation in the silicon layer, less than the first silicon thickness variation.
    Type: Application
    Filed: October 9, 2017
    Publication date: January 24, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Andrew M. Waite, Morgan D. Evans, John Hautala
  • Patent number: 10179958
    Abstract: An apparatus for forming a crystalline sheet. The apparatus may include a crystallizer comprising a first gas channel and a second gas channel, wherein the first gas channel and second gas channel extend through the crystallizer to a lower surface of the crystallizer between an upstream edge and a downstream edge. The first gas channel may be disposed closer to the downstream edge than the second gas channel. A first gas source may be coupled to the first gas channel, where the first gas source comprises helium or hydrogen, and a second gas source may be coupled to the second gas channel, where the second gas source does not contain hydrogen or helium.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: January 15, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC
    Inventors: Peter L. Kellerman, Brian D. Kernan, Frederick M. Carlson, Dawei Sun, David Morrell
  • Publication number: 20190006587
    Abstract: A method may include generating a plasma in a plasma chamber, the plasma comprising an etchant species and extracting a pulsed ion beam from the plasma chamber and directing the pulsed ion beam to a substrate, where the pulsed ion beam comprises an ON portion and an OFF portion. During the OFF portion the substrate may not be biased with respect to the plasma chamber, and the duration of the OFF portion may be less than a transit time of the etchant species from the plasma chamber to the substrate.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Glen F. R. Gilchrist, Raees Pervaiz, Kenneth Starks, Shurong Liang, Tyler Rockwell
  • Publication number: 20190006149
    Abstract: In one embodiment, an apparatus to treat a substrate may include an extraction plate to extract a plasma beam from a plasma chamber and direct the plasma beam to the substrate. The plasma beam may comprise ions forming a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate; and a gas outlet system disposed outside the plasma chamber, the gas outlet system coupled to a gas source and arranged to deliver to the substrate a reactive gas received from the gas source, wherein the reactive gas does not pass through the plasma chamber.
    Type: Application
    Filed: September 6, 2018
    Publication date: January 3, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Shurong Liang, Costel Biloiu, Glen Gilchrist, Vikram Singh, Christopher Campbell, Richard John Hertel, Alex Kontos