Abstract: An ion implanter and method for facilitating expeditious performance of maintenance on a component of the ion implanter in a manner that reduces downtime while increasing throughput of the ion implanter. The ion implanter includes a process chamber, a transfer chamber connected to the process chamber, a first isolation gate configured to controllably seal the transfer chamber from the process chamber, and a second isolation gate configured to controllably seal the transfer chamber from an atmospheric environment, wherein a component of the ion implanter can be transferred between the process chamber and the transfer chamber for performing maintenance on the component outside of the process chamber. Performing maintenance on a component of the ion implanter includes the steps of transferring the component from the process chamber to the transfer chamber, sealing the transfer chamber, venting the transfer chamber to atmospheric pressure, an opening the transfer chamber to an atmospheric environment.

Abstract: Provided herein are approaches for cooling a process chamber window. In some embodiments, a system for process chamber window cooling may include a process chamber for processing a wafer, wherein the process chamber includes a window. In some embodiments, the window allows light from a lamp assembly to be delivered to the wafer. The system further includes a cooling apparatus operable with the process chamber, the cooling apparatus for delivering a gas to the window. The cooling apparatus includes a support ring supporting the window. The support ring includes a perimeter wall, and a plurality of slots formed through the perimeter wall. The plurality of slots may deliver a gas (e.g., air) across the window.

Abstract: A method may include depositing a carbon layer on a substrate using physical vapor deposition, wherein the carbon layer exhibits compressive stress, and is characterized by a first stress value; and directing a dose of low-mass species into the carbon layer, wherein, after the directing, the carbon layer exhibits a second stress value, less compressive than the first stress value.

Abstract: A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device.

Abstract: An apparatus for monitoring of an ion beam. The apparatus may include a processor; and a memory unit coupled to the processor, including a display routine, where the display routine operative on the processor to manage monitoring of the ion beam. The display routine may include a measurement processor to receive a plurality of spot beam profiles of the ion beam, the spot beam profiles collected during a fast scan of the ion beam and a slow mechanical scan of a detector, conducted simultaneously with the fast scan. The fast scan may comprise a plurality of scan cycles having a frequency of 10 Hz or greater along a fast scan direction, and the slow mechanical scan being performed in a direction parallel to the fast scan direction. The measurement processor may also send a display signal to display at least one set of information, derived from the plurality of spot beam profiles.

Abstract: Provided herein are approaches for forming a conduit embedded within a component of a semiconductor manufacturing device (e.g., an ion implanter) using an additive manufacturing process (e.g., 3-D printing), wherein the conduit is configured to deliver a fluid throughout the component to provide heating, cooling, and gas distribution thereof. In one approach, the conduit includes a set of raised surface features formed on an inner surface of the conduit for varying fluid flow characteristics within the conduit. In another approach, the conduit may be formed in a helical configuration. In another approach, the conduit is formed with a polygonal cross section. In another approach, the component of the ion implanter includes at least one of an ion source, a plasma flood gun, a cooling plate, a platen, and/or an arc chamber base.

Abstract: An apparatus for controlling heat flow within a melt. The apparatus may include a crucible configured to contain the melt where the melt has an exposed surface. The apparatus may also include a heater disposed below a first side of the crucible and configured to supply heat through the melt to the exposed surface, and a heat diffusion barrier assembly comprising at least one heat diffusion barrier disposed within the crucible and defining an isolation region in the melt and an outer region in the melt.

Abstract: A foil liner comprising a plurality of foil layers is disclosed. The foil layers may each be an electrically conductive material that are stacked on top of each other. The spacing between adjacent foil layers may create a thermal gradient such that the temperature of the plasma is hotter than the temperature of the ion source chamber. In other embodiments, the foil layers may be assembly to sink the heat from the plasma so that the plasma is cooler than the temperature of the ion source chamber. In some embodiments, gaps or protrusions are disposed on one or more of the foil layers to affect the thermal gradient. In certain embodiments, one or more of the foil layers may be constructed of an insulating material to further affect the thermal gradient. The foil liner may be easily assembled, installed and replaced from within the ion source chamber.

Abstract: An apparatus for controlling heat flow within a melt. The apparatus may include a crucible configured to contain the melt where the melt has an exposed surface. The apparatus may also include a heater disposed below a first side of the crucible and configured to supply heat through the melt to the exposed surface, and a heat diffusion barrier assembly comprising at least one heat diffusion barrier disposed within the crucible and defining an isolation region in the melt and an outer region in the melt.

Abstract: Provided herein are approaches for in-situ plasma cleaning of one or more components of an ion implantation system. In one approach, the component may include a beam-line component, such as an energy purity module, having a plurality of conductive beam optics contained therein. The system further includes a power supply system for supplying a voltage and a current to the beam-line component during a cleaning mode, wherein the power supply system may include a first power plug coupled to a first subset of the plurality of conductive beam optics and a second power plug coupled to a second subset of the plurality of conductive beam optics. During a cleaning mode, the voltage and current may be simultaneously supplied and split between each of the first and second power plugs.

Abstract: Various nanostructures, including silicon nanowires and encapsulated silicon nanoislands, and methods of making the nanostructures are provided. The methods can include providing a fin structure extending above a substrate, wherein the fin structure has at least one silicon layer and at least two silicon:germanium alloy (SiGe) layers that define sidewalls of the fin structure; and annealing the fin structure in oxygen to form a silicon nanowire assembly. The silicon nanowire assembly can include a silicon nanowire, a SiGe matrix surrounding the silicon nanowire; and a silicon oxide layer disposed on the SiGe matrix. The annealing can be, for example, at a temperature between 800° C. and 1000° C. for five minutes to sixty minutes. The silicon nanowire can have a long axis extending along the fin axis, with perpendicular first and second dimensions extending less than 50 nm along directions perpendicular to the fin axis.

Abstract: A method of forming a semiconductor device. The method may include providing a device structure, where the device structure comprises a masked portion and a cut portion. The masked portion may comprise a mask covering at least one semiconductor fin of a fin array, and the cut portion may comprise a trench, where the trench exposes a semiconductor fin region of the fin array. The method may further include providing an exposure of the trench to oxidizing ions, the oxidizing ions to transform a semiconductor material into an oxide.

Abstract: A substrate assembly may include an outer halo, the outer halo comprising a first material and defining a first aperture. The substrate assembly may also include a halo ring, comprising a second material and disposed at least partially within the first aperture. The halo ring may define a second aperture, concentrically positioned within the first aperture, wherein the halo ring is coupled to accommodate a substrate therein.

Abstract: Methods herein may include forming trenches in a stack of layers atop a substrate, and forming a gate dielectric within the trenches. Methods may further include forming a first work function (WF) metal atop the gate dielectric, and forming a capping layer over the first WF metal using an angled ion implant deposition, the capping layer extending across the trenches. The first WF metal may be removed from just a first trench of the trenches, and a second WF metal is then formed over the stack of layers, wherein the second WF metal is formed atop the gate dielectric within the first trench. An angled ion etch may then be performed to recess the gate dielectric and the second WF metal within the first trench, and to recess the gate dielectric and the first WF metal within a second trench. A gate metal may then be formed within the trenches.

Abstract: Methods for forming three-dimensional transistor devices. In one embodiment a method of forming a three-dimensional transistor device may include providing a substrate comprising a semiconductor device structure, the semiconductor device structure comprising a nanowire stack, a gate stack disposed above the nanowire stack, and an inner spacer layer, disposed over the gate stack and the nanowire stack. The method may further include directing ions at the semiconductor device structure, wherein an altered layer is formed in a first part of the inner spacer layer, and an unaltered portion of the inner spacer layer remains, subjacent to the altered layer.

Abstract: A method includes providing a transistor structure, comprising a semiconductor fin and a plurality of gate structures, disposed on the semiconductor fin, forming an insulator layer on the transistor structure, and performing a lithographic process including an overlay shift, comprising defining a set of openings to be formed in the insulator layer. The set of openings define a shift in a first direction with respect to a midpoint between adjacent gate structures of the plurality of gate structures. The method includes etching the insulator layer using the plurality of openings, to form a trench region between a pair of adjacent gate structures, wherein a source/drain region between the pair of adjacent gate structures is exposed. The method includes performing an angled deposition of a dielectric coating, wherein the dielectric coating forms a coating on a first side of the trench, and not on a second side of the trench region.

Abstract: An apparatus for controlling and monitoring the lifetime of a superconducting fault current limiter. The apparatus may include a processor; and a memory unit coupled to the processor, including a lifetime routine, where the lifetime routine is operative on the processor to monitor the superconducting fault current limiter. The lifetime routine may include a lifetime estimation processor to receive a set of fault information for a fault event of a superconductor tape of the superconducting fault current limiter, determine a present state of the superconductor tape based upon the set of fault information, and determine an estimated lifetime of the superconductor tape based upon the present state. The present state may be determined from additional information such as fault history on the superconducting fault current limiter, as well as a database of superconductor tape behavior with respect to various faults.

Abstract: Embodiments herein include a halo having varied conductance. In some embodiments, a halo surrounding a semiconductor workpiece may include a first side opposite a second side, and a first end opposite a second end, wherein the first side is operable to receive an ion beam from an ion source. The halo may further include a plurality of apertures extending between the first side and the second side, wherein the plurality of apertures permit passage of a portion of the ion beam to pass therethrough, and wherein the halo has a varied conductance between the first and second ends. In some embodiments, at least a group of apertures of the plurality of apertures vary in at least one of: pitch, and diameter. In some embodiments, a thickness of the halo between the first side and the second side varies along a height extending between the first end and the second end.

Abstract: Embodiments of the disclosure provide a current protection device for a fault current limiter, the current protection device including a detection circuit electrically coupled between a current transformer and a pneumatic timer, and an electrical vacuum interrupter (EVI) coupled to a pneumatic cylinder. In some embodiments, the EVI includes a set of breaker contacts, wherein the pneumatic timer is communicatively coupled with the pneumatic cylinder to actuate a moveable contact of the set of breaker contacts. In some embodiments, the detection circuit is configured to detect a current of the current transformer, and to provide a control signal to the pneumatic cylinder to open or close the set of breaker contacts based on the detected current.

Abstract: Provided herein are approaches for reducing particles in an ion implanter. An electrostatic filter may include a housing and a plurality of conductive beam optics within the housing. The conductive beam optics are arranged around an ion beam-line directed towards a wafer, and may include entrance aperture electrodes proximate an entrance aperture of the housing. The conductive beam optics may further include energetic electrodes downstream along the ion beam-line from the entrance aperture electrodes, and ground electrodes downstream from the energetic electrodes. The energetic electrodes are positioned farther away from the ion beam-line than the entrance electrodes and the ground electrodes, thus causing the energetic electrodes to be physically blocked from impact by an envelope of back-sputter material returning from the wafer. The electrostatic filter may further include an electrical system for independently delivering a voltage and a current to each of the conductive beam optics.