Abstract: Provided herein are approaches for forming a gate dielectric layer for a DRAM device, the method including providing a substrate having a recess formed therein, the recess including a sidewall surface and a bottom surface. The method may further include performing an ion implant into just the bottom surface of the recess, and forming a gate dielectric layer along the bottom surface of the recess and along the sidewall surface of the recess. Once formed, a thickness of the gate dielectric layer along the sidewall surface is approximately the same as a thickness of the gate dielectric layer along the bottom surface of the recess. In some embodiments, the gate dielectric layer is thermally grown within the recess. In some embodiments, the ion implant is performed after a mask layer atop the substrate is removed.

Abstract: An optical grating component may include a substrate, and an optical grating, the optical grating being disposed on the substrate. The optical grating may include a plurality of angled structures, disposed at a non-zero angle of inclination with respect to a perpendicular to a plane of the substrate, wherein the plurality of angled structures are arranged to define a variable depth along a first direction, the first direction being parallel to the plane of the substrate.

Abstract: A method includes providing a substrate, where the substrate has a patterned substrate surface, wherein the patterned substrate surface comprises a first surface region and a second surface region. The method may also include directing a depositing species to the patterned substrate surface; and directing angled ions to the patterned substrate surface, wherein the depositing species forms a deposit on the first surface region and does not form a deposit on the second surface region.

Abstract: A method for forming a semiconductor device may include providing a transistor structure. The transistor structure may include a set of semiconductor fins and a set of gate structures, disposed on the set of semiconductor fins, wherein an isolation layer is disposed between the set of semiconductor fins and between the set of gate structures. The method may include implanting ions into an exposed area of the isolation layer, wherein an altered portion of the isolation layer is formed in the exposed area, wherein an altered region of the set of semiconductor fins is formed in an exposed portion of the set of semiconductor fins. The altered portion of the isolation layer may have a first etch rate, wherein an unaltered portion of the isolation layer, not exposed to the ions, has a second etch rate, greater than the first etch rate.

Abstract: A method may include providing a transistor structure on a substrate, where the transistor structure includes a semiconductor fin, a source/drain contact forming electrical contact with the semiconductor fin, and a gate conductor, disposed over the semiconductor fin, wherein the source drain contact and gate conductor are disposed in a trench. The method may further include directing angled ions to the trench, wherein the source/drain contact assumes a tapered shape.

Abstract: In one embodiment, a method of fabricating an electrostatic clamp includes forming an insulator body, forming an electrode on the insulator body, and depositing a layer stack on the electrode, the layer stack comprising an aluminum oxide layer that is deposited using atomic layer deposition (ALD).

Abstract: A method may include providing a surface feature on a substrate, the surface feature comprising a feature shape a feature location, and a dimension along a first direction within a substrate plane; depositing a layer comprising a layer material on the surface feature; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane, wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the surface feature and do not impact a second portion of the surface feature, and wherein an altered surface feature is generated, the altered surface feature differing from the surface feature in at least one of: the dimension along the first direction, the feature shape, or the feature location.

Abstract: A method of forming a three-dimensional transistor device may include performing a first blanket deposition of a first work function metal over a first nanowire stack, having a first polarity, and over a second nanowire stack having a second polarity, in a complementary metal oxide semiconductor (CMOS) nanosheet device structure, disposed on a substrate. The method may include directing angled oxygen ions at the CMOS nanosheet device structure. As a result an oxide may be formed in the first work function metal along a top region of the first nanowire stack and the second nanowire stack, while an oxide is not formed in the first work function metal at a bottom of a trench between the first nanowire stack and the second nanowire stack. The method may include performing a vertical etch to selectively remove the first work function metal between the first nanowire stack and the second nanowire stack.

Abstract: A method of forming an asymmetrical three dimensional semiconductor device. The method may include providing a fin structure extending perpendicularly from a substrate plane and having a fin axis parallel to the substrate plane, wherein a portion of the fin structure is covered by a gate structure defining a channel region, and wherein the fin structure comprises a first end surface not covered by the gate structure and second end surface not covered by the gate structure. The method may further include directing ions in a fin treatment to the fin structure, wherein the fin treatment comprises a first treatment of the first end surface and a second treatment of the second end surface different from the first treatment.

Abstract: Embodiments of the disclosure provide an apparatus and methods for localized stress modulation for overlay and substrate distortion using electron or ion implantation directly to a glass substrate. In one embodiment, a process for modifying a bulk property of a glass substrate generally includes identifying a stress pattern of a glass substrate, determining doping parameters to correct a defect (e.g., overlay error or substrate distortion) based on the stress pattern, and providing a treatment recipe to a treatment tool, wherein the treatment recipe is formulated according to the doping parameters. The process may further include performing a doping treatment process on the glass substrate using the treatment recipe to correct the overlay error or substrate distortion. In some embodiments, the treatment recipe is determined by comparing the stress pattern with a database library containing data correlating stress changes in glass substrates to various doping parameters.

Abstract: A superconducting fault current limiter element, comprising: a plurality of tapes, arranged in electrical parallel fashion among one another, wherein at least one tape of the plurality of tapes comprises a superconductor tape, and wherein at least one tape of the plurality of tapes comprises a non-superconductor tape.

Abstract: A method may include forming a sacrificial mask on a device structure, the sacrificial mask comprising a carbon-based material. The method may further include etching memory structures in exposed regions of the sacrificial mask, implanting an etch-enhancing species into the sacrificial mask, and performing a wet etch to selectively remove the sacrificial mask at etch temperature, less than 350° C.

Abstract: A lift pin system and a lift pin assembly are disclosed. In one or more approaches, a lift pin system includes a wafer support, such as an electrostatic chuck or a platen, and a lift pin assembly coupled to the wafer support. The lift pin assembly may include a plurality of pins. Each of the plurality of pins may include a tip extending through a housing, a spring within the housing, wherein the spring biases against the tip, and a support arm coupled to the housing. In some approaches, the housing is threadably coupled with the support arm to allow access to the tip of each pin above a top surface of the wafer support for easy replacement. The replaceable pin tips further permit easier customization of pin tip geometries, materials, spring force, etc., depending on specific process and/or wafer characteristics.

Abstract: Embodiments herein provide systems and methods for forming an optical component. A method may include providing a plurality of proximity masks between a plasma source and a workpiece, the workpiece including a plurality of substrates secured thereto. Each of the plurality of substrates may include first and second target areas. The method may further include delivering, from the plasma source, an angled ion beam towards the workpiece, wherein the angled ion beam is then received at one of the plurality of masks. A first proximity mask may include a first set of openings permitting the angled ion beam to pass therethrough to just the first target area of each of the plurality of substrates. A second proximity mask may include a second set of openings permitting the angled ion beam to pass therethrough just to the second target area of each of the plurality of substrates.

Abstract: A method may include forming a sacrificial mask on a device structure, the sacrificial mask comprising a carbon-based material. The method may further include etching memory structures in exposed regions of the sacrificial mask, implanting an etch-enhancing species into the sacrificial mask, and performing a wet etch to selectively remove the sacrificial mask at etch temperature, less than 350° C.

Abstract: A system and method for varying the temperature of a faceplate for an ion source is disclosed. The faceplate is held against the chamber walls of the ion source by a plurality of fasteners. These fasteners may include tension springs or compression springs. By changing the length of the tension spring or compression spring when under load, the spring force of the spring can be increased. This increased spring force increases the compressive force between the faceplate and the chamber walls, creating improved thermal conductivity. In certain embodiments, the length of the spring is regulated by an electronic length adjuster. This electronic length adjuster is in communication with a controller that outputs an electrical signal indicative of the desired length of the spring. Various mechanisms for adjusting the length of the spring are disclosed.

Abstract: An apparatus may include an electrode assembly, the electrode assembly comprising a plurality of electrodes, arranged in a plurality of electrode pairs arranged to conduct an ion beam therethrough. A given electrode pair lies along a radius of an arc describing a nominal central ray trajectory, wherein a radius of a first electrode pair and an adjacent electrode pair define an angular spacing. The plurality of electrode pairs may define a plurality of angular spacings, wherein, in a first configuration, the plurality of angular spacings are not all equal. The apparatus may also include a power supply in communication with the EM, the power supply configured to independently supply voltage to the plurality of electrodes.

Abstract: As etching processes become more aggressive, increased etch resistivity of the hard mask is desirable. Methods of modulating the etch rate of the mask and optionally the underlying material are disclosed. An etch rate modifying species is implanted into the hard mask after the mask etching process is completed. This etch rate modifying species increases the difference between the etch rate of the mask and the etch rate of the underlying material to help preserve the integrity of the mask during a subsequent etching process. In some embodiments, the etch rate of the mask is decreased by the etch rate modifying species. In certain embodiments, the etch rate of the underlying material is increased by the etch rate modifying species.

Abstract: A fault current limiter system including a fault current limiter and a variable shunt current splitting device. The current splitting device includes first and second conductive windings, wherein the first conductive winding is connected in parallel with the fault current limiter and is configured to carry current in a first direction. The second conductive winding is electrically connected in series with the fault current limiter and is configured to carry current in a second direction opposite to the first direction so that the reactance of the first winding is negated by the reactance of the second winding during steady state operation of the fault current limiter system. Thus, a first portion of a steady state current is conveyed through the fault current limiter and a second portion of the current is conveyed through the current splitting device. The steady state current load on the fault current limiter is thereby reduced.

Abstract: An extraction set including an extraction plate, a blocker and the holding mechanism for the blocker is disclosed. The extraction set includes an extraction plate that may be constructed of titanium coated with a ceramic material. The extraction plate is attached to the ion source using pins. The extraction plate also includes raised outline in its inner surface which is used to secure the blocker to the inner surface of the extraction plate. The ends of the blocker are secured by two holders disposed on opposite sides of the extraction aperture. The mechanism used for attaching the extraction plate to the ion source also improves the temperature uniformity of the extraction plate.