Abstract: A memory device may include an active device region, disposed at least partially in a first level. The memory device may include a storage capacitor, disposed at least partially in a second level, above the first level, wherein the first level and the second level are parallel to a substrate plane. The memory device may also include a contact via, the contact via extending between the storage capacitor and the active device region, and defining a non-zero angle of inclination with respect to a perpendicular to the substrate plane.

Abstract: A method includes providing a transistor structure, comprising a semiconductor fin and a plurality of gate structures, disposed on the semiconductor fin, forming an insulator layer on the transistor structure, and performing a lithographic process including an overlay shift, comprising defining a set of openings to be formed in the insulator layer. The set of openings define a shift in a first direction with respect to a midpoint between adjacent gate structures of the plurality of gate structures. The method includes etching the insulator layer using the plurality of openings, to form a trench region between a pair of adjacent gate structures, wherein a source/drain region between the pair of adjacent gate structures is exposed. The method includes performing an angled deposition of a dielectric coating, wherein the dielectric coating forms a coating on a first side of the trench, and not on a second side of the trench region.

Abstract: A method may include: providing a device stack, the device stack comprising sidewall portions and extending above a substrate base, the device stack further including a plurality of metal layers; depositing an interface layer conformally over the device stack using an atomic layer deposition process, the interface layer comprising a first insulator material; depositing an encapsulation layer on the interface layer, the encapsulation layer comprising a second insulator material; and depositing an interlevel dielectric disposed on the encapsulation layer, the interlevel dielectric comprising a third insulator material.

Abstract: A method for patterning a substrate, comprising: providing a photoresist patterning feature on the substrate, the substrate defining a substrate plane, the photoresist patterning feature having a softening temperature below 200° C. The method may include directing a first ion species into the photoresist patterning feature during a first exposure; and depositing a sidewall layer on the patterning feature after the directing at a deposition temperature, the deposition temperature being 200° C. or greater.

Abstract: An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer. The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region.

Abstract: An apparatus for the creation of high current ion beams is disclosed. The apparatus includes an ion source, such as a RF ion source or an indirectly heated cathode (IHC) ion source, having an extraction aperture. Disposed proximate the extraction aperture is a bias electrode, which has a hollow center portion that is aligned with the extraction aperture. A magnetic field is created along the perimeter of the hollow center portion, which serves to contain electrons within a confinement region. Electrons in the confinement region energetically collide with neutral particles, increasing the number of ions that are created near the extraction aperture. The magnetic field may be created using two magnets that are embedded in the bias electrode. Alternatively, a single magnet or magnetic coils may be used to create this magnetic field.

Abstract: An apparatus and method for the creation of negative ion beams is disclosed. The apparatus includes an RF ion source, having an extraction aperture. An antenna disposed proximate a dielectric window is energized by a pulsed RF power supply. While the RF power supply is actuated, a plasma containing primarily positive ions and electrons is created. When the RF power supply is deactivated, the plasma transforms into an ion-ion plasma. Negative ions may be extracted from the RF ion source while the RF power supply is deactivated. These negative ions, in the form of a negative ribbon ion beam, may be directed toward a workpiece at a specific incident angle. Further, both a positive ion beam and a negative ion beam may be extracted from the same ion source by pulsing the bias power supply multiple times each period.

Abstract: A plasma processing apparatus includes a process chamber housing defining a process chamber, a platen positioned in the process chamber for supporting a workpiece, a source configured to generate plasma in the process chamber, and a biasing system. The biasing system is configured to bias the platen with a negatively biased DC signal to attract ions from the plasma towards the workpiece during a first processing time interval and configured to bias the platen with a positively biased DC signal to repel ions from the platen towards interior surfaces of the process chamber housing during a cleaning time interval. The cleaning time interval is separate from the first processing time interval and occurs after the first processing time interval.

Abstract: An apparatus and methods of improving the ion beam quality of a halogen-based source gas are disclosed. Unexpectedly, the introduction of a noble gas, such as argon, to an ion source chamber may increase the percentage of desirable ion species, while decreasing the amount of contaminants and halogen-containing ions. This is especially beneficial in non-mass analyzed implanters, where all ions are implanted into the workpiece. In one embodiment, a first source gas, comprising a dopant and a halogen is introduced into an ion source chamber, a second source gas comprising a hydride, and a third source gas comprising a noble gas are also introduced. The combination of these three source gases produces an ion beam having a higher percentage of pure dopant ions than would occur if the third source gas were not used.

Abstract: An ion source having improved life is disclosed. In certain embodiments, the ion source is an IHC ion source comprising a chamber, having a plurality of electrically conductive walls, having a cathode which is electrically connected to the walls of the ion source. Electrodes are disposed on one or more walls of the ion source. A bias voltage is applied to at least one of the electrodes, relative to the walls of the chamber. In certain embodiments, fewer positive ions are attracted to the cathode, reducing the amount of sputtering experienced by the cathode. Advantageously, the life of the cathode is improved using this technique. In another embodiment, the ion source comprises a Bernas ion source comprising a chamber having a filament with one lead of the filament connected to the walls of the ion source.

Abstract: A method may include providing a substrate, the substrate comprising a substrate base and a patterning stack, disposed on the substrate base. The substrate may include first linear structures in the patterning stack, the first linear structures being elongated along a first direction; and second linear structures in the patterning stack, the second linear structures being elongated along a second direction, the second direction forming a non-zero angle with respect to the first direction. The method may also include selectively forming a set of sidewall spacers on one set of sidewalls of the second linear structures.

Abstract: Embodiments herein include a transparent halo assembly for reducing an amount of sputtered material to minimize particle defects impacting a workpiece. In some embodiments, a halo assembly may include a first halo arranged around a semiconductor workpiece, and a mounting assembly coupling the first halo to a roplat. The first halo may include a first side opposite a second side, and a first end opposite a second end, wherein the first side is operable to receive an ion beam from an ion source. The first halo may further include a plurality of apertures extending between the first and second sides, wherein the plurality of apertures permit passage of a portion of the ion beam to pass therethrough, towards the mounting assembly. In some embodiments, the halo assembly may include a second halo positioned proximate the first halo, and a third halo disposed between the first halo and the mounting assembly.

Abstract: An apparatus for monitoring of an ion beam. The apparatus may include a processor; and a memory unit coupled to the processor, including a display routine, where the display routine operative on the processor to manage monitoring of the ion beam. The display routine may include a measurement processor to receive a plurality of spot beam profiles of the ion beam, the spot beam profiles collected during a fast scan of the ion beam and a slow mechanical scan of a detector, conducted simultaneously with the fast scan. The fast scan may comprise a plurality of scan cycles having a frequency of 10 Hz or greater along a fast scan direction, and the slow mechanical scan being performed in a direction parallel to the fast scan direction. The measurement processor may also send a display signal to display at least one set of information, derived from the plurality of spot beam profiles.

Abstract: Embodiments herein include a halo having varied conductance. In some embodiments, a halo surrounding a semiconductor workpiece may include a first side opposite a second side, and a first end opposite a second end, wherein the first side is operable to receive an ion beam from an ion source. The halo may further include a plurality of apertures extending between the first side and the second side, wherein the plurality of apertures permit passage of a portion of the ion beam to pass therethrough, and wherein the halo has a varied conductance between the first and second ends. In some embodiments, at least a group of apertures of the plurality of apertures vary in at least one of: pitch, and diameter. In some embodiments, a thickness of the halo between the first side and the second side varies along a height extending between the first end and the second end.

Abstract: In one embodiment, an apparatus to selectively deposit a carbon layer on substrate, comprising a plasma chamber to receive a flow of carbon-containing gas; a power source to generate a plasma containing the carbon-containing gas in the plasma chamber; an extraction plate to extract an ion beam from the plasma and direct the ion beam to the substrate, the ion beam comprising ions having trajectories forming a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate, the extraction plate further configured to conduct a neutral species derived from the carbon-containing gas to the substrate; and a substrate stage facing the extraction plate and including a heater to heat the substrate to a first temperature, when the ion beam and carbon-containing species impinge on the substrate.

Abstract: A system for implanting ions into a workpiece while minimizing the generation of particles is disclosed. The system includes an ion source having an extraction plate with an extraction aperture. The extraction plate is electrically biased and may also be coated with a dielectric material. The workpiece is disposed on a platen and surrounded by an electrically biased shield. The shield may also be coated with a dielectric material. In operation, a pulsed DC voltage is applied to the shield and the platen, and ions are attracted from the ion source during this pulse. Since a pulsed voltage is used, the impedance of the thin dielectric coating is reduced, allowing the system to function properly.

Abstract: In one embodiment a vacuum assembly for an ion implanter system includes a first turbomolecular pump operatively coupled to a source chamber of the ion implanter system and a first backing line having a first end and a second end, the first end coupled to an exhaust port of the first turbomolecular pump, wherein the first turbomolecular pump and first end of the first backing line are configured to operate at a voltage potential of the source chamber. The vacuum assembly further includes a voltage insulator that is insulatively coupled to the first backing line, and a second turbomolecular pump operatively coupled to the first backing line, wherein the second turbomolecular pump is configured to operate at ground voltage potential.

Abstract: An apparatus of a wafer processing apparatus includes at least one memory and logic, at least a portion of which is implemented in circuitry of the wafer processing apparatus including at least one processor coupled to the at least one memory. The logic may provide a 3D model of a surface of a wafer, the wafer defining a wafer plane; and modify a surface feature in a Z-direction along the surface of the wafer based on at least one of: an X-critical dimension (CD) extending along an X-direction of the wafer plane, and a Y-CD extending along a Y direction of the wafer plane.

Abstract: A fault current limiter may include a current limiting leg to transmit a first current and a control leg in parallel with the current limiting leg, the control leg to transmit a second current. The control leg may include a plurality of power electronic modules arranged in electrical series with one another, and a bypass power electronic module arranged in electrical series with the plurality of power electronic modules. The control leg may further include a plurality of current monitors arranged electrically in series with the plurality of power electronic modules and the bypass power electronic module, and at least one triggering circuit, wherein the plurality of current monitors is electrically coupled to the at least one triggering circuit, and wherein the at least one triggering circuit is coupled to at least one of: the plurality of power electronic modules, and the bypass power electronic module.

Abstract: An ion source with improved temperature control is disclosed. A portion of the ion source is nestled within a recessed cavity in a heat sink, where the portion of the ion source and the recessed cavity are each shaped so that expansion of the ion source causes high pressure thermal contact with the heat sink. For example, the ion source may have a tapered cylindrical end, which fits within a recessed cavity in the heat sink. Thermal expansion of the ion source causes the tapered cylindrical end to press against the recessed cavity in the heat sink. By proper selection of the temperature of the heat sink, the temperature and flow of coolant fluid through the heat sink, and the size of the gap between the heat sink and the ion source, the temperature of the ion source can be controlled.