Patents Assigned to Varian Semiconductor Equipment Associates, Inc.
  • Filling a cavity in a substrate using sputtering and deposition
    Patent number: 10546730
    Abstract: A method may include providing a cavity in a surface of a substrate, the cavity comprising a sidewall portion and a lower surface; directing depositing species to the surface of the substrate, wherein the depositing species condense to form a fill material on the sidewall portion and lower surface; and directing angled ions at the cavity at a non-zero angle of incidence with respect to a perpendicular to a plane defined by the substrate, wherein the angled ions strike an exposed part of the sidewall portion and do not strike the lower surface, and wherein the cavity is filled by the fill material in a bottom-up fill process.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: January 28, 2020
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC
    Inventors: Simon Ruffell, John Hautala
  • TECHNIQUES, SYSTEM AND APPRATUS FOR SELECTIVE DEPOSITION OF A LAYER USING ANGLED IONS
    Publication number: 20200027707
    Abstract: A method is provided. The method may include providing a substrate, the substrate comprising a substrate surface, the substrate surface having a three-dimensional shape. The method may further include directing a depositing species from a deposition source to the substrate surface, wherein a layer is deposited on a deposition region of the substrate surface. The method may include performing a substrate scan during the directing or after the directing to transport the substrate from a first position to a second position. The method may also include directing angled ions to the substrate surface, in a presence of the layer, wherein the layer is sputter-etched from a first portion of the deposition region, and wherein the layer remains in a second portion of the deposition region.
    Type: Application
    Filed: July 17, 2018
    Publication date: January 23, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: CHRISTOPHER HATEM, KEVIN ANGLIN
  • METHOD AND DEVICE FOR POWER RAIL IN A FIN TYPE FIELD EFFECT TRANSISTOR
    Publication number: 20200027777
    Abstract: A method of forming a semiconductor device may include providing a semiconductor device structure. The semiconductor device structure may include semiconductor fins pitched at a fin pitch on a substrate and a mask, disposed over the semiconductor fins, the mask defining a plurality of openings. The semiconductor device structure may further include an isolation oxide disposed on the substrate, between the semiconductor fins. The method may further include directing angled ions into the at least one of the plurality of openings. The angled ions may form at least one trench between at least one pair of the semiconductor fins, in the substrate below the isolation oxide between the at least one pair of the semiconductor fins. Furthermore, a width within the substrate of the at least one trench is greater than a minimum fin pitch and greater than a width of the at least one trench above the substrate.
    Type: Application
    Filed: July 17, 2018
    Publication date: January 23, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Min Gyu Sung
  • DIRECTIONAL DEPOSITION FOR PATTERNING THREE-DIMENSIONAL STRUCTURES
    Publication number: 20200027733
    Abstract: A method for patterning a three-dimensional structure is provided. The method may include providing a substrate, the substrate including the three-dimensional structure, and directing a depositing species from a deposition source to the three-dimensional structure, wherein a layer forms on the three-dimensional structure. The method may further include directing angled ions to the three-dimensional structure from an ion source, wherein the angled ions impinge on a first region of the layer and do not impinge on a second region of the layer. As such, the first region may form a densified layer portion having a first density, and the second region may form an undensified layer portion having a second density, less than the first density.
    Type: Application
    Filed: July 20, 2018
    Publication date: January 23, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventor: JOHN HAUTALA
  • DEVICE STRUCTURE AND TECHNIQUES FOR FORMING SEMICONDUCTOR DEVICE HAVING ANGLED CONDUCTORS
    Publication number: 20200027832
    Abstract: A method of forming a device may include forming a component in a first level of a device structure; forming a contact cavity overlapping the component, the contact cavity forming a non-zero angle of inclination with respect to a perpendicular to a substrate plane. The method may further include filling the contact cavity with a conductor, wherein an angled conductor is formed, wherein the angled conductor extends to a second level of the device structure.
    Type: Application
    Filed: July 17, 2018
    Publication date: January 23, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Sony Varghese, Anthony Renau, Morgan Evans, John Hautala, Joe Olson, Min Gyu Sung
  • GATE SPACER FORMATION FOR SCALED CMOS DEVICES
    Publication number: 20200027795
    Abstract: Disclosed are methods of forming a CMOS device. One non-limiting method may include providing a gate structure atop a substrate, and forming a first spacer over the gate structure. The method may include removing the first spacer from just an upper portion of the gate structure by performing an angled reactive ion etch or angled implantation disposed at a non-zero angle of inclination with respect to a perpendicular to a plane of the substrate. The method may further include forming a second spacer over the upper portion of the gate structure and the first spacer along a lower portion of the gate structure. A thickness of the first spacer and the second spacer along the lower portion of the gate structure may be greater than a thickness of the second spacer along the upper portion of the gate structure.
    Type: Application
    Filed: July 17, 2018
    Publication date: January 23, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Min Gyu Sung, Sony Varghese
  • APPARATUS AND TECHNIQUES FOR BEAM MAPPING IN ION BEAM SYSTEM
    Publication number: 20200027698
    Abstract: An apparatus for monitoring of an ion beam. The apparatus may include a processor; and a memory unit coupled to the processor, including a display routine, where the display routine operative on the processor to manage monitoring of the ion beam. The display routine may include a measurement processor to receive a plurality of spot beam profiles of the ion beam, the spot beam profiles collected during a fast scan of the ion beam and a slow mechanical scan of a detector, conducted simultaneously with the fast scan. The fast scan may comprise a plurality of scan cycles having a frequency of 10 Hz or greater along a fast scan direction, and the slow mechanical scan being performed in a direction parallel to the fast scan direction. The measurement processor may also send a display signal to display at least one set of information, derived from the plurality of spot beam profiles.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Eric D. Wilson, George M. Gammel, Sruthi Chennadi, Daniel Tieger, Shane Conley
  • Method and apparatus for non line-of-sight doping
    Patent number: 10541137
    Abstract: A method of doping a substrate. The method may include providing a substrate in a process chamber. The substrate may include a semiconductor structure, and a dopant layer disposed on a surface of the semiconductor structure. The method may include maintaining the substrate at a first temperature for a first interval, the first temperature corresponding to a vaporization temperature of the dopant layer. The method may further include rapidly cooling the substrate to a second temperature, less than the first temperature, and heating the substrate from the second temperature to a third temperature, greater than the first temperature.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: January 21, 2020
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Christopher R. Hatem, Piero Sferlazzo, Roger Fish, Dale K. Stone
  • INCREASED ISOLATION OF DIFFUSION BREAKS IN FINFET DEVICES USING AN ANGLED ETCH
    Publication number: 20200020570
    Abstract: Methods for forming semiconductor devices herein may include forming a trench in a substrate layer, wherein a hardmask is disposed atop the substrate layer, and implanting the trench at an angle relative to a top surface of the hardmask. The method may further include forming an oxide layer within the trench, wherein a thickness of the oxide layer along a bottom portion of the trench is greater than a thickness of the oxide layer along an upper portion of the trench.
    Type: Application
    Filed: July 16, 2018
    Publication date: January 16, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Min Gyu Sung, Sony Varghese
  • ELECTROSTATIC ELEMENT HAVING GROOVED EXTERIOR SURFACE
    Publication number: 20200020508
    Abstract: Provided herein are approaches for increasing surface area of a conductive beam optic by providing grooves or surface features thereon. In one approach, the conductive beam optic may be part of an electrostatic filter having a plurality of conductive beam optics disposed along an ion beam-line, wherein at least one conductive beam optic includes a plurality of grooves formed in an exterior surface. In some approaches, a power supply may be provided in communication with the plurality of conductive beam optics, wherein the power supply is configured to supply a voltage and a current to the plurality of conductive beam optics. The plurality of grooves may be provided in a spiral pattern along a length of the conductive beam optic, and/or oriented parallel to a lengthwise axis of the conductive beam optic.
    Type: Application
    Filed: March 19, 2018
    Publication date: January 16, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Eric Hermanson, Philip Layne, James Alan Pixley
  • SYSTEM AND METHOD FOR OPTIMALLY FORMING GRATINGS OF DIFFRACTED OPTICAL ELEMENTS
    Publication number: 20200018981
    Abstract: Optical grating components and methods of forming are provided. In some embodiments, a method includes providing an etch stop layer atop a substrate, and providing an optical grating layer atop the etch stop layer. The method may further include providing a patterned mask layer over the optical grating layer, and etching the optical grating layer and the patterned mask layer to form an optical grating in the optical grating layer. The optical grating may include a plurality of angled components, disposed at a non-zero angle of inclination with respect to a perpendicular to a plane of the substrate, wherein the etching forms an area of over-etch in the etch stop layer between the plurality of angled components.
    Type: Application
    Filed: July 13, 2018
    Publication date: January 16, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Morgan Evans, Rutger Meyer Timmerman Thijssen, Joseph Olson, Peter Kurunczi
  • SYSTEM AND METHOD FOR OPTIMALLY FORMING GRATINGS OF DIFFRACTED OPTICAL ELEMENTS
    Publication number: 20200018985
    Abstract: Optical grating components and methods of forming are provided. In some embodiments, a method includes providing an optically transparent substrate, and forming an optical grating layer on the substrate. The method includes forming an optical grating in the optical grating layer, wherein the optical grating comprises a plurality of angled components, disposed at a non-zero angle of inclination with respect to a perpendicular to a plane of the substrate. A first sidewall of the optical grating may have a first angle, and a second sidewall of the grating has a second angle different than the first angle. Modifying process parameters, including selectivity and beam angle spread, has an effect of changing a shape or dimension of the plurality of angled components.
    Type: Application
    Filed: July 13, 2018
    Publication date: January 16, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Morgan Evans, Rutger Meyer Timmerman Thijssen, Joseph Olson, Peter Kurunczi
  • Varied component density for thermal isolation
    Patent number: 10535499
    Abstract: A system that utilizes a component that controls thermal gradients and the flow of thermal energy by variation in density is disclosed. Methods of fabricating the component are also disclosed. The component is manufactured using additive manufacturing. In this way, the density of different regions of the component can be customized as desired. For example, a lattice pattern may be created in the interior of a region of the component to reduce the amount of material used. This reduces weight and also decreases the thermal conduction of that region. By using low density regions and high density regions, the flow of thermal energy can be controlled to accommodate the design constraints.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: January 14, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Adam M. McLaughlin, Craig R. Chaney
  • Angular control of ion beam for vertical surface treatment
    Patent number: 10535522
    Abstract: Provided herein are techniques for treating vertical surface features of a semiconductor device with ions. In some embodiments, a method for forming a semiconductor device, may include providing a set of surface features extending from a substrate, the set of surface features including a sidewall. The method may include treating the sidewall with an ion beam disposed at an angle, the angle being a non-zero angle of inclination with respect to a perpendicular to a plane of an upper surface of the substrate. The method may further include rotating the substrate about the perpendicular to the plane while the sidewall is treated with the ion beam to impact an entire height of the sidewall with the ion beam.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: January 14, 2020
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Gang Shu, Glen Gilchrist, Shurong Liang
  • Apparatus for forming crystalline sheet from a melt
    Patent number: 10526720
    Abstract: An apparatus for drawing a crystalline sheet from a melt. The apparatus may include a crucible configured to contain the melt and having a dam structure, where the melt comprises an exposed surface having a level defined by a top of the dam structure. The apparatus may further include a support apparatus disposed within the crucible and having an upper surface, wherein the crystalline sheet is maintained flush with the exposed surface of the melt when drawn over the support apparatus, and may include a melt-back heater directing heat through the upper surface of the support apparatus to partially melt the crystalline sheet when the crystalline sheet is drawn over the support apparatus.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: January 7, 2020
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Dawei Sun, Peter L. Kellerman, Gregory Thronson
  • In-situ plasma cleaning of process chamber components
    Patent number: 10522330
    Abstract: Provided herein are approaches for in-situ plasma cleaning of one or more components of an ion implantation system. In one approach, the component may include a beam-line component having one or more conductive beam optics. The system further includes a power supply for supplying a first voltage and first current to the component during a processing mode and a second voltage and second current to the component during a cleaning mode. The second voltage and current may be applied to the conductive beam optics of the component, in parallel, to selectively (e.g., individually) generate plasma around one or more of the one or more conductive beam optics. The system may further include a flow controller for adjusting an injection rate of an etchant gas supplied to the component, and a vacuum pump for adjusting pressure of an environment of the component.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: December 31, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Kevin Anglin, William Davis Lee, Peter Kurunczi, Ryan Downey, Jay T. Scheuer, Alexandre Likhanskii, William M. Holber
  • Uniform gate dielectric for DRAM device
    Patent number: 10522549
    Abstract: Provided herein are approaches for forming a gate dielectric layer for a DRAM device, the method including providing a substrate having a recess formed therein, the recess including a sidewall surface and a bottom surface. The method may further include performing an ion implant into just the bottom surface of the recess, and forming a gate dielectric layer along the bottom surface of the recess and along the sidewall surface of the recess. Once formed, a thickness of the gate dielectric layer along the sidewall surface is approximately the same as a thickness of the gate dielectric layer along the bottom surface of the recess. In some embodiments, the gate dielectric layer is thermally grown within the recess. In some embodiments, the ion implant is performed after a mask layer atop the substrate is removed.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: December 31, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Baonian Guo, Qintao Zhang
  • TECHNIQUES FOR FORMING DUAL EPITAXIAL SOURCE/DRAIN SEMICONDUCTOR DEVICE
    Publication number: 20190393094
    Abstract: A method of forming a three-dimensional transistor device. The method may include providing a transistor structure, where the transistor structure includes a fin assembly, a gate assembly, the gate assembly disposed over the fin assembly and comprising a plurality of gates, a liner layer, disposed over the plurality of gates, and an isolation layer, disposed subjacent the liner layer. The method may also include directing first angled ions at the transistor device, wherein a first altered liner layer is created in the liner layer, wherein, in the presence of a liner-removal etchant, the liner layer exhibits a first etch rate, the first altered liner layer exhibits a second etch rate, greater than the first etch rate.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 26, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Min Gyu Sung, Rajesh Prasad
  • Techniques for forming low stress mask using implantation
    Patent number: 10515802
    Abstract: A method may include depositing a mask layer on a substrate using physical vapor deposition, wherein an absolute value of a stress in the mask layer has a first value; and directing a dose of ions into the mask layer, wherein the absolute value of the stress in the mask layer has a second value, less than the first value, after the directing the dose.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: December 24, 2019
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Rajesh Prasad, Tzu-Yu Liu, Edwin Arevalo, Deven Mittal, Somchintana Norasetthekul, Kyuha Shim, Lauren Liaw, Takaski Shimizu, Nobuyuki Sasaki, Ryuichi Muira, Hiro Ito
  • Structure and method of forming fin device having improved fin liner
    Patent number: 10510610
    Abstract: A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: December 17, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee