Patents Assigned to Varian Semiconductor Equipment Associates, Inc.
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Patent number: 10633743Abstract: A system and method for removing metal from a substrate in a controlled manner is disclosed. The system includes a chamber, with one or more gas inlets to allow the flow of gasses into the chamber, at least one exhaust pump, to exhaust gasses from the chamber, and a heater, capable of modifying the temperature of the chamber. In some embodiments, one or more gasses are introduced into the chamber at a first temperature. The atoms in these gasses chemically react with the metal on the surface of the substrate to form a removable compound. The gasses are then exhausted from the chamber, leaving the removable compound on the surface of the substrate. The temperature of the chamber is then elevated to a second temperature, greater than the sublimation temperature of the removable compound. This increased temperature allows the removable compound to become gaseous and be exhausted from the chamber.Type: GrantFiled: May 16, 2018Date of Patent: April 28, 2020Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Tsung-Liang Chen, Benjamin Schmiege, Jeffrey W. Anthis, Glen Gilchrist
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Publication number: 20200126757Abstract: Provided herein are approaches for in-situ plasma cleaning of ion beam optics. In one approach, a system includes a component (e.g., a beam-line component) of an ion implanter processing chamber. The system further includes a power supply for supplying a first voltage and first current to the component during a processing mode and a second voltage and second current to the component during a cleaning mode. The second voltage and current are applied to one or more conductive beam optics of the component, individually, to selectively generate plasma around one or more of the one or more conductive beam optics. The system may further include a flow controller for adjusting an injection rate of an etchant gas supplied to the beam-line component, and a vacuum pump for adjusting pressure of an environment of the beam-line component.Type: ApplicationFiled: December 23, 2019Publication date: April 23, 2020Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Kevin Anglin, William Davis Lee, Peter Kurunczi, Ryan Downey, Jay T. Scheuer, Alexandre Likhanskii, William M. Holber
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Patent number: 10629437Abstract: A method may include providing a substrate, comprising a patterning layer. The method may include forming a first pattern of first linear structures in the patterning layer, the first linear structures being elongated along a first direction. The method may include forming a mask over the patterning layer, the mask comprising a second pattern of second linear structures, elongated along a second direction, forming a non-zero angle with respect to the first direction. The method may include selectively removing a portion of the patterning layer while the mask is in place, wherein a first etch pattern is formed in the patterning stack, the first etch pattern comprising a two-dimensional array of cavities. The method may include directionally etching the first etch pattern using an angled ion beam, wherein a second etch pattern is formed, comprising the two-dimensional array of cavities, elongated along the first direction.Type: GrantFiled: August 30, 2018Date of Patent: April 21, 2020Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Sony Varghese, John Hautala, Steven R. Sherman, Rajesh Prasad, Min Gyu Sung
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Patent number: 10607999Abstract: A method may include providing a substrate, the substrate comprising a substrate base and a patterning stack, disposed on the substrate base. The substrate may include first linear structures in the patterning stack, the first linear structures being elongated along a first direction; and second linear structures in the patterning stack, the second linear structures being elongated along a second direction, the second direction forming a non-zero angle with respect to the first direction. The method may also include selectively forming a set of sidewall spacers on one set of sidewalls of the second linear structures.Type: GrantFiled: November 3, 2017Date of Patent: March 31, 2020Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Sony Varghese, Naushad Variam
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Publication number: 20200098579Abstract: A method may include forming in a substrate a first array of a first material of first linear structures, interspersed with a second array of a second material, of second linear structures, the first and second linear structures elongated along a first axis. The method may include generating a chop pattern in the first layer, comprising a third linear array, interspersed with a fourth linear array. The third and fourth linear arrays may be elongated along a second axis, forming a non-zero angle of incidence with respect to the first axis. The third linear array may include alternating portions of the first and second material, while the fourth linear array comprises an array of cavities, arranged within the patterning layer. The method may include elongating a first set of cavities along the first axis, to form a first set of elongated cavities bounded by the first material.Type: ApplicationFiled: January 18, 2019Publication date: March 26, 2020Applicant: Varian Semiconductor Equipment Associates, Inc.Inventor: Sony Varghese
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Publication number: 20200096870Abstract: A method of patterning a substrate may include providing a blanket photoresist layer on the substrate; performing an ion implantation procedure of an implant species into the blanket photoresist layer, the implant species comprising an enhanced absorption efficiency at a wavelength in the extreme ultraviolet (EUV) range; and subsequent to the performing the ion implantation procedure, performing a patterned exposure to expose the blanket photoresist layer to EUV radiation.Type: ApplicationFiled: November 22, 2019Publication date: March 26, 2020Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Tristan Y. Ma, Huixiong Dai, Anthony Renau, John Hautala, Joseph Olson
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Publication number: 20200098589Abstract: Disclosed are methods for removing bridge defects using an angled implant and selective photoresist etch. In one embodiment, a method includes providing a semiconductor device including plurality of photoresist lines on a stack of layers, wherein a bridge defect extends between two or more photoresist lines of the plurality of photoresist lines. The method may further include implanting a sidewall and an upper surface of the two or more photoresist lines with an ion beam disposed at an angle, the angle being a non-zero angle of inclination with respect to a perpendicular to a plane of the upper surface of the stack of layers. The method may further include etching the semiconductor device to remove the bridge defect.Type: ApplicationFiled: September 25, 2018Publication date: March 26, 2020Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Tristan Y. MA, Juiyuan Hsu
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Publication number: 20200098540Abstract: In one embodiment, an ion extraction optics for extracting a plurality of ion beams is provided. The ion extraction optics may include, an extraction plate, the extraction plate defining a cut-out region, the cut-out region being elongated along a first direction. The extraction apparatus may include a slidable insert, the slidable insert disposed to overlap the cut-out region, and slidably movable with respect to the extraction plate, along the first direction, wherein the slidable insert and cut-out region define a first aperture and a second aperture.Type: ApplicationFiled: September 23, 2019Publication date: March 26, 2020Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Costel Biloiu, Jon Ballou, James P. Buonodono
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Patent number: 10598832Abstract: Embodiments herein provide systems and methods for forming an optical component. A method may include providing a plurality of proximity masks between a plasma source and a workpiece, the workpiece including a plurality of substrates secured thereto. Each of the plurality of substrates may include first and second target areas. The method may further include delivering, from the plasma source, an angled ion beam towards the workpiece, wherein the angled ion beam is then received at one of the plurality of masks. A first proximity mask may include a first set of openings permitting the angled ion beam to pass therethrough to just the first target area of each of the plurality of substrates. A second proximity mask may include a second set of openings permitting the angled ion beam to pass therethrough just to the second target area of each of the plurality of substrates.Type: GrantFiled: January 9, 2018Date of Patent: March 24, 2020Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Morgan Evans, Rutger Meyer Timmerman Thijssen, Joseph Olson, Peter Kurunczi, Robert Masci
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Patent number: 10600675Abstract: A method may include providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising an insulator layer and a silicon layer. The silicon layer may be disposed on the insulator layer, where the silicon layer comprises a first silicon thickness variation. The method may include forming an oxide layer on the silicon layer, where the oxide layer has a uniform thickness. The method may include selectively etching the oxide layer on the silicon layer, wherein the oxide layer comprises a first non-uniform oxide thickness. After thermal processing of the SOI substrate in an oxygen ambient, the non-uniform oxide thickness may be configured to generate a second silicon thickness variation in the silicon layer, less than the first silicon thickness variation.Type: GrantFiled: October 9, 2017Date of Patent: March 24, 2020Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Andrew M. Waite, Morgan D. Evans, John Hautala
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Patent number: 10600616Abstract: In one embodiment, an apparatus to treat a substrate may include an extraction plate to extract a plasma beam from a plasma chamber and direct the plasma beam to the substrate. The plasma beam may comprise ions forming a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate; and a gas outlet system disposed outside the plasma chamber, the gas outlet system coupled to a gas source and arranged to deliver to the substrate a reactive gas received from the gas source, wherein the reactive gas does not pass through the plasma chamber.Type: GrantFiled: September 6, 2018Date of Patent: March 24, 2020Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Shurong Liang, Costel Biloiu, Glen Gilchrist, Vikram Singh, Christopher Campbell, Richard John Hertel, Alex Kontos
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Patent number: 10600662Abstract: A system and method for heating silicon carbide substrates is disclosed. The system includes a heating element that utilizes LEDs that emit light at wavelengths between 600 nm and 650 nm. This wavelength is better absorbed by silicon carbide. In certain embodiments, collimating optics are disposed between the LEDs and the silicon carbide substrate. The collimating optics may increase the allowable distance between the LEDs and the substrate. In other embodiments, a diffuser is disposed between the LEDs and the substrate. In addition, a method of heating a substrate is disclosed. The relationship between absorption coefficient and wavelength is determined for the substrate. Based on this relationship, an optimal wavelength or range of wavelengths is selected. The substrate is then heated using an LED emitting light at the optimal wavelengths.Type: GrantFiled: July 20, 2018Date of Patent: March 24, 2020Assignee: Varian Semiconductor Equipment Associates, Inc.Inventor: Paul E. Pergande
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Publication number: 20200090982Abstract: A method of forming a semiconductor device. The method may include providing a semiconductor device structure. The semiconductor device structure may include a semiconductor fin; and a mask, disposed over the semiconductor fin, the mask defining a plurality of openings, wherein the semiconductor fin is exposed in the plurality of openings. The method may further include directing angled ions into the plurality of openings, wherein a plurality of trenches are formed in the semiconductor fin, wherein a given trench of the plurality of trenches comprises a reentrant profile.Type: ApplicationFiled: November 25, 2019Publication date: March 19, 2020Applicant: Varian Semiconductor Equipment Associates, Inc.Inventor: Min Gyu Sung
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Publication number: 20200090909Abstract: A method may include providing a cavity in a surface of a substrate, the cavity comprising a sidewall portion and a lower surface; directing depositing species to the surface of the substrate, wherein the depositing species condense to form a fill material on the sidewall portion and lower surface; and directing angled ions at the cavity at a non-zero angle of incidence with respect to a perpendicular to a plane defined by the substrate, wherein the angled ions strike an exposed part of the sidewall portion and do not strike the lower surface, and wherein the cavity is filled by the fill material in a bottom-up fill process.Type: ApplicationFiled: November 22, 2019Publication date: March 19, 2020Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Simon Ruffell, John Hautala
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Publication number: 20200083027Abstract: Disclosed is a semiconductor processing apparatus including one or more components having a conductive or nonconductive foam material. In some embodiments, the component is a plasma flood gun including a shield assembly coupled to the plasma flood gun. The shield assembly may include a first shield having a first main side facing an ion beam target, and a connection block coupled to a second main side of the first shield. The shield assembly may further include a mounting plate coupled to the connection block, and a second shield coupled to the mounting plate by a bracket. In some embodiments, the first shield and/or one or more process chamber walls includes a foam material, such as a conductive or nonconductive foam.Type: ApplicationFiled: October 16, 2018Publication date: March 12, 2020Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: James Alan Pixley, Eric D. Hermanson, Philip Layne, Lyudmila Stone, Thomas Stacy
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Publication number: 20200083021Abstract: Disclosed is a semiconductor processing apparatus including one or more components having a conductive or nonconductive porous material. In some embodiments, an ion implanter may include a plurality of beam line components for directing an ion beam to a target, and a porous material along a surface of at least one of the plurality of beamline components.Type: ApplicationFiled: August 26, 2019Publication date: March 12, 2020Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: James Alan Pixley, Eric D. Hermanson, Philip Layne, Lyudmila Stone, Thomas Stacy
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Publication number: 20200066486Abstract: An apparatus may include a first grounded drift tube, arranged to accept a continuous ion beam, at least two AC drift tubes, arranged in series, downstream to the first grounded drift tube, and a second grounded drift tube, downstream to the at least two AC drift tubes. The apparatus may include an AC voltage assembly, electrically coupled to at least two AC drift tubes. The AC voltage assembly may include a first AC voltage source, coupled to deliver a first AC voltage signal at a first frequency to a first AC drift tube of at least two AC drift tubes. The AC voltage assembly may further include a second AC voltage source, coupled to deliver a second AC voltage signal at a second frequency to a second AC drift tube of the at least two AC drift tubes, wherein the second frequency comprises an integral multiple of the first frequency.Type: ApplicationFiled: August 21, 2018Publication date: February 27, 2020Applicant: Varian Semiconductor Equipment Associates, Inc.Inventor: Frank Sinclair
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Patent number: 10569299Abstract: A system that reduces the amount of water that enters a process chamber via a movable shaft is disclosed. The surface of the shaft is made hydrophobic. Any water droplets that are collected on the hydrophobic shaft are disposed at a high contact angle, making it more likely that these water droplets fall from the shaft. Further, any water that enters the process chamber is more readily removed from the shaft due to the lower energy of liberation. Reducing the amount of water in a process chamber may improve the lifetime of the components in the process chamber and may improve the yield of the workpieces being processed. This may be especially relevant when process gasses that contain halogens are employed.Type: GrantFiled: March 30, 2018Date of Patent: February 25, 2020Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Ernest E. Allen, Jr., Jonathan David Fischer, Jeffrey E. Krampert
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Patent number: 10553448Abstract: A method of processing a layer. The method may include providing the layer on a substrate, the substrate defining a substrate plane; directing an ion beam to an exposed surface of the layer in an ion exposure when the substrate is disposed in a first rotational position, the ion beam having a first ion trajectory, the first ion trajectory extending along a first direction, wherein the first ion trajectory forms a non-zero angle of incidence with respect to a perpendicular to the substrate plane; performing a rotation by rotating the substrate with respect to the ion beam about the perpendicular from the first rotational position to a second rotational position; and directing the ion beam to the exposed surface of the layer in an additional ion exposure along the first ion trajectory when the substrate is disposed in the second rotational position.Type: GrantFiled: October 31, 2016Date of Patent: February 4, 2020Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Tristan Y. Ma, Morgan Evans, Kevin Anglin, Robert J. Masci, John Hautala
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Patent number: 10546770Abstract: A method of forming a semiconductor device. The method may include providing a semiconductor device structure. The semiconductor device structure may include a semiconductor fin; and a mask, disposed over the semiconductor fin, the mask defining a plurality of openings, wherein the semiconductor fin is exposed in the plurality of openings. The method may further include directing angled ions into the plurality of openings, wherein a plurality of trenches are formed in the semiconductor fin, wherein a given trench of the plurality of trenches comprises a reentrant profile.Type: GrantFiled: May 2, 2018Date of Patent: January 28, 2020Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventor: Min Gyu Sung