Abstract: A system for fast determination of a horizontal minimum of multiple digital values including a difference circuit and a compare circuit. The difference circuit may include first and second adders in which the first adder compares upper bits of a first digital value with upper bits of a second digital value and provides a first carry output and a propagate output. The second adder compares lower bits of the first digital value with lower bits of the second digital value and provides a second carry output. The compare circuit determines whether the first digital value is greater than the second digital value based on the carry and propagate outputs. Multiple difference circuits may be used to compare each of multiple digital values with every other digital value to provide corresponding compare bits, which are then used to determine a minimum one of the digital values and its corresponding location.

Abstract: A system which uses common adder circuitry to perform either one of a horizontal minimum instruction and a sum of absolute differences instruction including multiple adders, a sum circuit, a compare circuit, and a routing circuit. The input operands include multiple digital values which are delivered by the routing circuit to the adders depending upon which instruction is indicated. Each adder determines a difference between a pair of digital values. The differences are grouped and summed together by the sum circuit for the sum of absolute differences instruction. The adders are paired together for the horizontal minimum instruction, in which each pair provides carry and propagate outputs. The upper portions of a pair of digital values are compared by the upper adder and the lower portions are compared by the lower adder, and the carry and propagate outputs are collectively used to determine the minimum value.

Abstract: A method for reading non-standard register of Serial Advanced Technology Attachment (SATA) devices discloses an unused input parameter of standard command setting up as an executive parameter. While receiving the standard command, a SATA host controller converts the executive parameter and the standard command into input frame information structure (FIS) that is sent to the SATA devices for the SATA devices to detect the executive parameter for reading corresponding value of non-standard register and saving the value into an output register of the SATA devices. The value of the non-standard register is converted into output frame information structure for being sent to the SATA host controller and the value of the non-standard register is saved to the output register of the SATA host controller. Then by reading the value of the output register of the SATA host controller, the value of the non-standard register is learned.

Abstract: Determining and simultaneously using a circuit for a mobile device couple to a base station, the circuit may comprise an identification signal detector for receiving a first identification signal corresponding to a first module and a second identification signal corresponding to a second module in the mobile device. The circuit may comprise a receiver for receiving a plurality of signals from the base station; said plurality of signals is configured to set up communication between the mobile device and the base station. The circuit may comprise a calculator for calculating a plurality of parameters in response to the first identification signal, second identification signal and said plurality of signals received from said base station.

Abstract: A USB host controller is provided. The USB host controller is capable of communicating with multiple USB apparatuses having endpoints and sends a request to a first endpoint. The USB host controller includes a first storage and a first control unit. The first control unit stores endpoint information from the first endpoint into the first storage when the first endpoint issues an unready transaction packet in response to the request. The unready transaction packet indicates that the first endpoint is not ready.

Abstract: The invention provides a new linked structure for a buffer controller and management method thereof. The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

Abstract: The invention provides a packet error detecting method for a serial link. When a start framing symbol of a packet appears at the serial link, the start framing symbol is ignore if a predetermined error condition is satisfied.

Abstract: A USB peripheral device and a method of determining USB speed mode. The method of determining USB speed mode for an USB peripheral device, wherein the USB peripheral device is coupled to an USB host through an USB transmission cable, and the USB transmission cable comprises power and ground lines for power supply, and first and second data signals for transmitting data, the method comprising the USB peripheral device pulling up voltage level of the first data signal with a first pull-up device, the USB peripheral device pulling up voltage level of the second data signal with a second pull-up device, and the USB host determining a high/full speed mode for the USB peripheral device, when detecting only one of the first and second data signals exceeding a threshold, and then detecting the other data signal exceeding the threshold in a predetermined period.

Abstract: An optimum power calibration method is provided and is implemented for writing a rewritable optical storage medium including a power calibration area. The method includes the steps of determining whether the power calibration area is recorded with data, erasing the entire power calibration area when the power calibration area is not recorded, and executing an optimum power calibration procedure. In addition, the optimum power calibration method is applied to a rewritable optical disk drive.

Abstract: The present invention described a test method for unit re-modification, in which there is a test end and a host end. The method generated a sample pattern at a test end, generates a control pattern and modifies a re-modification unit. Otherwise, an experimental pattern is generated and then whether or not the original function is retained after modifying the re-modification unit is determined according to the result of comparison of the control pattern and experimental pattern thereon. The present invention is used to test the internal function module of specific software or hardware, and ensure that the proper function is retained after re-modification.

Abstract: The present invention is directed to a neighbor cell synchronization method for a mobile communication unit. The method includes selecting a neighbor cell according to a scheduling mechanism; determining a synchronization window according to a communicating mode of the mobile communication unit; and searching or decoding specific logic channels within the synchronization window. The present invention also provides an apparatus for performing the method.

Abstract: An embodiment of a computer system comprises a south-bridge. The south-bridge comprises a controller including a buffer for communicating with electronic devices. When detecting that a Reset# signal is asserted, the buffer is set to a Hi-Impedance state to separate the controller from the electronic device. The Reset# signal indicates a full system reset.

Abstract: The present invention provides an apparatus and method for performing cryptographic operations on a plurality of message blocks within a processor to generate a message digest. In one embodiment, the apparatus has an x86-compatible microprocessor that includes translation logic and execution logic. The translation logic receives a single, atomic cryptographic instruction from a source therefrom, where the single, atomic cryptographic instruction prescribes generation of the message digest according to one of the cryptographic operations. The translation logic also translates the single, atomic cryptographic instruction into a sequence of micro instructions specifying sub-operations required to accomplish generation of the message digest according to the one of the cryptographic operations. The execution logic is operatively coupled to the translation logic. The execution logic receives the sequence of micro instructions, and performs the sub-operations to generate the message digest.

Abstract: An x86-compatible microprocessor that executes an application program fetched from memory, including a single, atomic hash instruction directing the x86-compatible microprocessor to perform the hash operation. The single, atomic hash instruction has an opcode field and a repeat prefix field. The opcode field prescribes that the x86-compatible microprocessor accomplish the hash operation. The repeat prefix field is coupled to the opcode field and indicates that the hash operation prescribed by the single, atomic hash instruction is to be accomplished on one or more message blocks. The x86-compatible microprocessor has a hash unit that is configured to execute a plurality of hash computations on each of the one or more message blocks to generate a corresponding intermediate hash value, where a last intermediate hash value that is computed for a last message block after processing all previous message blocks includes a message digest corresponding to the one or more message blocks.

Abstract: A microprocessor including a substrate bias rail providing a bias voltage during a first operating mode, a supply node providing a core voltage, a clamp device coupled between the bias rail and the supply node, and control logic. The control logic turns on the clamp device to clamp the bias rail to the supply node during a second operating mode and turns off the clamp device during the first operating mode. The clamp devices may be implemented with P-channel and N-channel devices. Level shift and buffer circuits may be provided to control the clamp devices based on substrate bias voltage levels. The microprocessor may include a substrate with first and second areas each including separate substrate bias rails. The control logic separately turns on and off clamp devices to selectively clamp the substrate bias rails in the first and second areas based on various power modes.

Abstract: A turbo decoder includes first and second interleavers, a de-interleaver, first and second component decoders and a stop judging circuit. The first and second component decoders respectively decode a systematic code and an interleaved systematic code into first and second extrinsic information. The de-interleaver, the first and second data interleavers respectively process the second extrinsic information, the systematic code and the first extrinsic information into a first a-priori information, an interleaved systematic code and the second a-priori information. The stop judging circuit includes a signal selector, a difference detector and a comparator. The signal selector outputs the first extrinsic information and the first a-priori information or the second extrinsic information and the second a-priori information.

Abstract: An x87 fused multiply-add (FMA) instruction in the instruction set of an x86 architecture microprocessor is disclosed. The FMA instruction implicitly specifies the two factor operands as the top two operands of the x87 FPU register stack and explicitly specifies the third addend operand as a third x87 FPU register stack register. The microprocessor multiplies the first two operands and adds the product to the third operand to generate a result. The result is stored into the third register and the first two operands are popped off the stack. In an alternate embodiment, the third operand is also implicitly specified as being stored in the register that is two registers below the top of stack register; the result is also stored therein. The instruction opcode value is in the x87 opcode range.

Abstract: The present invention relates to an expandable structure for peripheral storage devices. The expandable structure includes an interface controller having a plurality of connecting ports for serial data transmission; and a Port Multiplier electrically connected to one of the connecting ports of the interface controller for serial data transmission, and the Port Multiplier having a plurality of expanded connecting ports, wherein each of the expanded connecting ports is capable of connecting to a peripheral storage device with a parallel data transmission mode or a peripheral storage device with a serial data transmission mode.

Abstract: Provided is a system for compressing multiple-sample-anti-aliasing (MSAA) tile data in a computer graphics pipeline. The system includes a plurality of pixels configured as a tile, where the tile has a plurality of samples of descriptor data for the pixels. Multiple graphics data processing units configured to receive the plurality of samples contain a plurality of coverage masks, which correspond to covered subtiles and compression logic encodes the tile descriptor data for receipt by a buffer.

Abstract: A switch circuit for switching two clock signals includes a clock generator, a flip-flop and a multiplexer. The clock generator is to generate a reference signal whose cycle is the lowest common multiple of the cycles of the two clock signals. The flip-flop is to generate a selecting signal by taking a control signal from system as an input signal and taking the reference signal as a timing trigger signal. The multiplexer can output a selected clock signal according to the selecting signal in which the selected clock signal and the switched clock signal are synchronous during their entire cycles.