Patents Assigned to VIA Technologies
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Publication number: 20100180104Abstract: A microprocessor has a microcode memory for storing original microcode instructions to implement user program instructions, and an interface to an external memory for storing a microcode patch. The microcode patch includes substitute microcode instructions and validation information. The microprocessor includes a private random access memory (PRAM), addressable by the original and substitute microcode instructions but not addressable by user program instructions. The microprocessor also includes patch hardware, which conditionally receives the substitute microcode instructions. The microprocessor executes the substitute microcode instructions when applied to the patch hardware instead of corresponding original microcode instructions.Type: ApplicationFiled: March 13, 2009Publication date: July 15, 2010Applicant: VIA Technologies, Inc.Inventors: G. Glenn Henry, Terry Parks
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Patent number: 7756991Abstract: A data-packet processing method is used in a network system. The network system includes a buffer for optionally storing a data packet to be transferred, and the method includes steps of: determining a type of the data packet to be transferred; determining a storage state of a buffer where the data packet is to be temporarily stored before transferring; and storing the data packet into the buffer if the storage state of the buffer is a packet-accepting storage state; wherein the packet-accepting storage state of the buffer varies with the type of the data packet.Type: GrantFiled: December 7, 2007Date of Patent: July 13, 2010Assignee: Via Technologies, Inc.Inventors: Wei-Pin Chen, Edward Ku, Yun-Fei Chao
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Patent number: 7757031Abstract: A data transmission coordinating method is used between a central processing unit and a bridge chip of a computer system. By entering the computer system into a coordinating state, the data transmission coordinating method is executed. The bridge chip and the CPU are informed of maximum bit numbers of each other for data transmission therebetween via the front side bus. Then, a commonly operable maximum bit number for data transmission between the CPU and the bridge chip can be coordinated according to the first and second maximum bit numbers. Once the commonly operable maximum bit number is determined, the CPU is reset to operate with the commonly operable maximum bit number. The maximum bit numbers are those of bus transmission width or bus transmission speed.Type: GrantFiled: October 22, 2007Date of Patent: July 13, 2010Assignee: Via Technologies, Inc.Inventors: Ruei-Ling Lin, Jiin Lai
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Patent number: 7755632Abstract: A GPU pipeline is synchronized by sending a fence command from a first module to an addressed synchronization register pair. Fence command associated data may be stored in a fence register of the addressed register pair. A second module sends a wait command with associated data to the addressed register pair, which may be compared to the data in the fence register. If the fence register data is greater than or equal to the wait command associated data, the second module may be acknowledged for sending the wait command and released for processing other graphics operations. If the fence register data is less than the wait command associated data, the second module is stalled until subsequent receipt of a fence command having data that is greater than or equal to the wait command associated data, which may be written to a wait register associated to the addressed register pair.Type: GrantFiled: October 25, 2006Date of Patent: July 13, 2010Assignee: VIA Technologies, Inc.Inventors: John Brothers, Hsilin Huang, Boris Prokopenko
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Patent number: 7757130Abstract: RAID control of multiple hard disk drives in a computer system includes performing a fault-tolerant data computing operation for a written data. The timing for performing the fault-tolerant data computing operation is determined by accessing a data stored in one of the hard disk drives, detecting a partial data length of a data stream having been transmitted from the hard disk drive to the computer system, issuing a triggering signal when the data length has reached a unitary length less than the total length of the data stream, and then performing the fault-tolerant data computing operation with the unitary length of data in response to the triggering signal.Type: GrantFiled: August 9, 2007Date of Patent: July 13, 2010Assignee: Via Technologies, Inc.Inventor: Kuan-Jui Ho
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Patent number: 7755083Abstract: A package module with an alignment structure is provided by this invention. The package module comprises a package substrate having a die region and a die disposed thereon. At least one pair of conductive alignment protrusions is disposed in the die region and is separated from each other by the die. A test pad is disposed on the package substrate opposing the die and electrically connected to the pair of conductive alignment protrusions. An electronic device with an alignment structure and an inspection method after mounting is also disclosed.Type: GrantFiled: March 1, 2006Date of Patent: July 13, 2010Assignee: Via Technologies, Inc.Inventor: Chih-Hsiung Lin
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Patent number: 7752647Abstract: Systems and methods for rearranging valid data within a block of data for transmission along a data path are described herein. By utilizing previously unused bits in data words, the valid data can be transmitted in fewer clock cycles, thereby increasing the availability of the data bus to other masters. An exemplary embodiment of a system for transmitting data along a data bus includes one or more masters, one or more slaves, and a data bus interconnecting the masters and slaves. One of the slaves is a memory controller configured to access data from an external memory device. The memory controller may be further configured to pack video data for transmission along the data bus. One of the masters is a video display controller configured to feed video data to an external video display. The video display controller may be further configured to receive the packed video data and unpack the packed video data for transmission to the video display.Type: GrantFiled: August 29, 2006Date of Patent: July 6, 2010Assignee: Via Technologies, Inc.Inventor: Hon Chung Fung
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Patent number: 7750784Abstract: An inductor structure includes a winding turn layer, a shielding layer, and a number of vias. The winding turn layer disposed above a substrate is formed by a number of turns connected in series and t has a first end and a second end. The first end is grounded. The shielding layer disposed between the winding turn layer and the substrate has a third end and a fourth end. At least two turns starting from the first end of the winding turn layer are projected onto the shielding layer. The vias are disposed between the winding turn layer and the shielding layer to at least electrically connect the third end and the fourth end of the shielding layer to a first turn of the winding turn layer. The first turn starts from the first end, and the winding turn layer and the shielding layer are electrically coupled in parallel.Type: GrantFiled: December 19, 2008Date of Patent: July 6, 2010Assignee: VIA Technologies, Inc.Inventor: Sheng-Yuan Lee
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Patent number: 7747883Abstract: A computer system with a non-support hyper-transport processor and a controlling method of a hyper-transport bus thereof. The computer system includes a system management controller, a Northbridge, a hyper-transport bus, a central processing unit and a power management signal line. The Northbridge is electrically connected to the system management controller through the hyper-transport bus. The central processing unit is electrically connected to the Northbridge, and the central processing unit does not support the hyper-transport bus. The system management controller outputs a power management signal to the central processing unit and the Northbridge through the power management signal line so that the hyper-transport bus changes from a first working frequency to a second working frequency, and from a first bus width to a second bus width.Type: GrantFiled: March 5, 2007Date of Patent: June 29, 2010Assignee: Via Technologies, Inc.Inventor: Ming-Wei Hsu
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Patent number: 7746818Abstract: The present invention provides a single circuit and a method which can identify the WLAN standard of a packet or the modulation type of a packet. The single circuit includes a shift register, N determinators and decision logic. The shift register is configured to receive several periods of the preamble of the packet. Each of the N determinators is configured to determine whether the WLAN standard, or the modulation type, of the packet matches one of the N WLAN standards, or the N modulation types. Decision logic is configured to decide the WLAN standard, or the modulation type, of the packet.Type: GrantFiled: November 24, 2004Date of Patent: June 29, 2010Assignee: VIA Technologies, Inc.Inventors: Kai Pon Kao, Chih Chia Wang
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Patent number: 7746744Abstract: An optical recording system and a control method thereof. The method includes detecting a target signal level. If the change level of the target signal exceeds a tolerant range, it represents that a shock has occurred. The shock frequency is recorded according to the shock, and the tolerant range is adjusted according to the recorded shock frequency. If the change level of the target signal exceeds the tolerant range, a pick-up head stops writing data into the optical storage medium. If the change level of the target signal is less than or equal to the tolerant range, the pick-up head writes data into the optical storage medium.Type: GrantFiled: January 3, 2006Date of Patent: June 29, 2010Assignee: Via Technologies, Inc.Inventor: Szu-Lien Chu
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Patent number: 7742061Abstract: Method and related apparatus for image processing. When projecting a polygonal object in three-dimensional space onto a two-dimensional screen according to a viewing range, faces of the object which intersect boundaries of the viewing range are clipped to form clipped planes. Vertices of all of the clipped planes of the object are recorded in one vertex list according to a triangle-list primitive, so as to increase efficiency of the image processing.Type: GrantFiled: October 26, 2006Date of Patent: June 22, 2010Assignee: VIA Technologies Inc.Inventor: Yi-Peng Chen
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Patent number: 7743179Abstract: Data transmission systems and methods. The data transmission system comprises a bus, a slave, a master, and a master interface. The master transmits a request comprising transfer information comprising a start address and a length. The master interface receives the request from the master. The master interface determines a burst type of a first burst according to the transfer information, and transmits the first burst with the burst type to the slave via the bus, where the first burst is aligned to at least one address boundary of the slave. The master interface receives data corresponding to the first burst from the slave, and transmits the data to the master.Type: GrantFiled: March 30, 2007Date of Patent: June 22, 2010Assignee: Via Technologies, Inc.Inventors: Dejian Li, Wenbin Li
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Patent number: 7741872Abstract: A level shifter for shifting an input signal to an output signal. The level shifter includes an input buffer biased a first voltage and a ground voltage; an output buffer and a level-processing unit both biased between a second voltage and the ground voltage; and a voltage-drop unit coupled to the level-processing unit and biased between the first voltage and the second voltage. While the first voltage is in an OFF state and the second voltage is switched on, the voltage-drop unit provides an initializing voltage for the level-processing unit according to the second voltage to shift the input signal to provide the output signal.Type: GrantFiled: February 14, 2008Date of Patent: June 22, 2010Assignee: Via Technologies, Inc.Inventor: Chao-Sheng Huang
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Patent number: 7742679Abstract: A method for choosing the first candidate to be loaded from a series of job requests for a mix mode multimedia player is disclosed. A job table having a plurality of rows is provided. Each row for a job has a job message with a “Priority” status, a “Usage status” status, and an “Examining function” status. The jobs are generated by a loader manager module of the mix mode multimedia player according to the job requests. The job messages of the jobs are arranged according to the “Priority” status in order. Then, the first candidate is chosen according to the following steps. The “Usage status” status of the job message is examined. If the “Usage status” is “used”, the “Examining function” status of the job message is examined. At last, If the “Examining function” status is “Critical”, the job is set as the first candidate.Type: GrantFiled: July 21, 2006Date of Patent: June 22, 2010Assignee: Via Technologies, Inc.Inventor: Scot Lee
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Patent number: 7737983Abstract: A method for high level synchronization between an application and a graphics pipeline comprises receiving an application instruction in an input stream at a predetermined component, such as a command stream processor (CSP), as sent by a central processing unit. The CSP may have a first portion coupled to a next component in the graphics pipeline and a second portion coupled to a plurality of components of the graphics pipeline. A command associated with the application instruction may be forwarded from the first portion to the next component in the graphics pipeline or some other component coupled thereto. The command may be received and thereafter executed. A response may be communicated on a feedback path to the second portion of the CSP. Nonlimiting exemplary application instructions that may be received and executed by the CSP include check surface fault, trap, wait, signal, stall, flip, and trigger.Type: GrantFiled: October 25, 2006Date of Patent: June 15, 2010Assignee: Via Technologies, Inc.Inventors: John Brothers, Timour Paltashev, Hsilin Huang, Boris Prokopenko, Qunfeng (Fred) Liao
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Patent number: 7733129Abstract: A memory clock signal is generated in response to a reference clock signal and a clock enable signal. The memory clock signal with a frequency identical to that of the reference clock signal is generated during the clock enable signal is in an enabled state; and the memory clock signal with a reduced frequency is generated when the clock enable signal is changed from the enabled state to a disabled state. The generation of a memory clock signal is adaptive so as to save power.Type: GrantFiled: July 3, 2008Date of Patent: June 8, 2010Assignee: Via Technologies, Inc.Inventor: Chi Chang
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Patent number: 7729456Abstract: The present invention discloses a burst detection apparatus and method. The burst detection apparatus of the present invention comprises a power module, a soft-metric RMS module, and a quality determination module. The bust detection method comprises the following steps: At first, a reciprocal value of the received signal's power is calculated. Next, a RMS value of the soft-metrics according to the received signal is computed. At last, a product of the reciprocal value and the RMS value is compared with a given threshold value to generate a Boolean outcome as a quality determination decision. If the product of these values is lower than the given threshold value, it means the received signal is believed as noise; otherwise, it is believed as the real signal.Type: GrantFiled: November 17, 2004Date of Patent: June 1, 2010Assignee: Via Technologies, Inc.Inventor: LiJun Zhang
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Patent number: 7730337Abstract: A power saving method is disclosed. A halt instruction is issued to enable transition from an operational state to a power saving state. The processor broadcasts a message to a chipset. The chipset receives the sleep message and enters a power saving state, and asserts a hardware pin to disable a data bus connecting the processor and the chipset. It is determined whether a request for data transaction required during the power saving process is issued to the chipset. If the request is issued to the chipset, the chipset deasserts the hardware pin to enable the data bus, transmits the request to the processor; and, when data transaction is complete, asserts the hardware pin by the chipset to disable the data bus.Type: GrantFiled: January 24, 2007Date of Patent: June 1, 2010Assignee: VIA Technologies, Inc.Inventor: Jen-Chieh Chen
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Publication number: 20100131783Abstract: A system and method of dynamically switching the threshold of a data queue, such as FIFO, is disclosed. The data queue has a first threshold and a second threshold, wherein the first threshold is greater than the second threshold. The data queue is dynamically switched between the first threshold and the second threshold according to different power state of a central processing unit (CPU). A system memory is requested to fill the data queue with data whenever amount of the data queue is less than the switched first/second threshold.Type: ApplicationFiled: November 24, 2008Publication date: May 27, 2010Applicant: Via Technologies, Inc.Inventors: Chih-Hao Weng, Ta-Jung Yeh