Patents Assigned to VIA Technologies
-
Patent number: 7783905Abstract: A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.Type: GrantFiled: June 13, 2006Date of Patent: August 24, 2010Assignee: Via Technologies Inc.Inventors: Nai-Shung Chang, Chia-Hsing Yu
-
Patent number: 7777326Abstract: A routing structure of an RDL of a chip is provided. The routing structure comprises a power route, a plurality of first stripes, a ground route, and a plurality of second stripes. The power route is arranged in a first direction and comprises a plurality of first bumps and a plurality of first line segments. Each of the first line segments connects adjacent first bumps. The first stripes are arranged in a second direction and connected to the power route. The ground route is disposed at one side of the power route in a third direction, and comprises a plurality of second bumps and a plurality of second line segments. Each of the second line segments connects adjacent second bumps. The second stripes, are arranged in a forth direction and connected to the ground route. The first stripes and the second stripes are interleaved without intersecting one another.Type: GrantFiled: September 10, 2008Date of Patent: August 17, 2010Assignee: VIA Technologies, Inc.Inventor: Xiaoshan Chen
-
Patent number: 7779083Abstract: A message transmitting queue delivers messages between a source controller and a destination controller. According to the message transmitting request of the source controller, sequentially distribute the free message row of the message transmitting queue, and set the message row to the distributed state. After the source controller writes the message of the message row, set the message row to the written state. At this moment, when the message row is in the position that is read sequentially by the destination controller, a read request is issued, so that the destination controller reads the message according to the read request when the reading completes, clears the distributed signal and the written signal, so that the message row goes back to the free state. When the message transmitting queue has no free message row, a no free message row signal to inform the source controller is issued.Type: GrantFiled: November 15, 2002Date of Patent: August 17, 2010Assignee: Via Technologies, Inc.Inventors: Wei-Pin Chen, Chun-Hua Tseng
-
Patent number: 7779314Abstract: System and related method for testing a chip with a high-speed bus interface in a low speed testing environment is provided. The testing method for testing input/output functions of a chip includes: establishing an inner loop path between a transmission mechanism and a receiving mechanism of the chip; transmitting a testing data; and receive the testing data via the inner loop path.Type: GrantFiled: December 25, 2006Date of Patent: August 17, 2010Assignee: VIA Technologies Inc.Inventor: Chun-Yuan Su
-
Patent number: 7779215Abstract: A method for utilizing the multi-channel transmission bandwidth in an asymmetrically arranged memory is provides. The present invention defines symmetrically arranged parts of the memory ranks of the memory as a virtual ranks. If data is stored in symmetrically arranged memory ranks of the memory, channels corresponding to the symmetrically arranged memory ranks could be simultaneously utilized to transfer data. If data is stored in an asymmetrically arranged memory rank of the memory, the channel corresponding to the asymmetrically arranged memory rank could only be utilized to transfer data.Type: GrantFiled: March 4, 2005Date of Patent: August 17, 2010Assignee: VIA Technologies Inc.Inventors: Ming-Shi Liou, Bowei Hsieh, Jiin Lai
-
Patent number: 7778525Abstract: A method of preventing playing of audio or video data from being interrupted for a mix mode multimedia playback system comprises the following steps: a video stream buffer, a audio stream buffer, and a parser module is provided; then amount of free space in the video stream buffer is checked so as to ensure the amount of the free space is larger than a sum of a track buffer and video data being processed by the parser module. Whenever the playing of an audio scene state machine is paused or stopped, audio data processed by the parser module and audio data in the track buffer are pushed into the free space of the audio stream buffer so as to release entire space of the track buffer for video data to be loaded.Type: GrantFiled: July 20, 2006Date of Patent: August 17, 2010Assignee: Via Technologies, Inc.Inventor: Scot Lee
-
Patent number: 7779400Abstract: Firmware of an optical storage medium device includes an executable program code and at least one reference data set. A method for modifying the firmware without requiring a compiling process includes inputting an attribute data set for setting a user interface; modifying the firmware by modifying the reference data set according to the attribute data set, wherein the executable program code is not modified when the firmware is being modified; determining if the modified firmware is capable of performing a target operation before the modified firmware is written into the optical storage medium device, wherein the user interface can be displayed according to the attribute data set; displaying the user interface according to the attribute data set; and writing the modified firmware into the optical storage medium device after the modified firmware is capable of performing the target operation.Type: GrantFiled: December 5, 2005Date of Patent: August 17, 2010Assignee: VIA Technologies Inc.Inventors: Willy Chuang, Jakie Yeh, Shangen Wang, Jonathan Lin
-
Patent number: 7778364Abstract: A signal strength estimation circuit for a code division multiple access system comprises a channel compensator, a demodulator, an extractor and an average circuit. The channel compensator compensates different channel effect upon a received signal and outputs first and second compensated signals wherein the received signal comprises a first signal and a second signal. The demodulator electrically connected to the channel compensator demodulates the first and second compensated signals and outputs first and second demodulated signals wherein the demodulator demodulates the first and second compensated signals by corresponding 4 bits pilot patterns when each of the first and second compensated signals only has 2 pilot bits in a slot and the second signal is obtained by space time transmit diversity encoding the first signal. The extractor coupled to the demodulator respectively extracts first and second pilot signals from the first and second demodulated signals.Type: GrantFiled: July 26, 2007Date of Patent: August 17, 2010Assignee: Via Technologies, Inc.Inventors: Chih-Chiu Wang, Huoy-Bing Lim
-
Publication number: 20100205406Abstract: An out-of-order execution microprocessor executes an architectural segment register-loading instruction that instructs the microprocessor to load a new value into an architectural segment register of the microprocessor. A comparator compares the new value specified by the architectural segment register-loading instruction with a current contents of the architectural segment register. A control unit causes to be re-executed using the new value all instructions in the microprocessor that used the current architectural segment register contents as a source operand and that are newer in program order than the architectural segment register-loading instruction whenever the comparator indicates the new value does not equal the current contents.Type: ApplicationFiled: February 11, 2009Publication date: August 12, 2010Applicant: VIA Technologies, Inc..Inventors: Rodney E. Hooker, Gerard M. Col, Terry Parks
-
Publication number: 20100205404Abstract: A microprocessor includes a memory that stores instructions of a non-user program to implement a user program instruction of the user-visible instruction set of the microprocessor. The non-user program includes a conditional branch instruction. A first fetch unit fetches instructions of the user program that includes the instruction that is implemented by the non-user program. An instruction decoder decodes the user program instructions and saves a state in response to decoding the user program instruction that is implemented by the non-user program. An execution unit executes the user program instructions fetched by the first fetch unit and executes instructions of the non-user program other than the conditional branch instruction. A second fetch unit fetches the non-user program instructions from the memory and resolves the conditional branch instruction based on the saved state without sending the conditional branch instruction to the execution unit to resolve the conditional branch instruction.Type: ApplicationFiled: June 9, 2009Publication date: August 12, 2010Applicant: VIA Technologies, Inc.Inventors: G. Glenn Henry, Terry Parks, Brent Bean
-
Patent number: 7774629Abstract: A method for power management of a CPU and a system thereof, which drive the CPU to enter a more efficient power saving state are disclosed. A chip of the present invention sends a first control signal to drive the CPU to wake from a non-snooping sleep state and enter a normally executing instruction state as well as a system management mode to execute a system management interrupt routine. Then the chip enables an arbiter to transmit a bus master request to the CPU for processing. After completing the processing of the bus master request, the chip disables the arbiter and the CPU drives the chip to send a second control signal to drive the CPU to return to the non-snooping sleep state according the system management interrupt routine.Type: GrantFiled: November 28, 2006Date of Patent: August 10, 2010Assignee: Via Technologies, Inc.Inventors: Wen-Juin Huang, Chung-Chin Huang, Cheng-Wei Huang, Jui-Ming Wei
-
Patent number: 7774627Abstract: A temperature sensor in a microprocessor monitors its operating temperature Operating point data includes a first temperature being the maximum temperature at which the microprocessor will reliably operate at a first frequency and first voltage, the first frequency being the maximum frequency at which the microprocessor will reliably operate at the first temperature and the first voltage. Operating point data also includes a second temperature at which the microprocessor will reliably operate at a second frequency and a second voltage, the second frequency being greater than the first frequency and the second temperature less than the first temperature. A control circuit causes the microprocessor to operate at the second voltage and frequency rather than the first voltage and frequency in response to detecting that while operating at the first voltage and the first frequency the operating temperature dropped below the second temperature.Type: GrantFiled: June 11, 2007Date of Patent: August 10, 2010Assignee: VIA Technologies, Inc.Inventors: Darius D. Gaskins, Stephan Gaskins
-
Patent number: 7768918Abstract: A method for expanding a service VLAN space of a provider network is provided. A bit number occupied by a taq protocol identifier (TPID) in a TPID field is reduced to leave a plurality of spare bits. The spare bits of the TPID field is then used to represent a first portion of a service VLAN identifier. A VLAN identifier field of a tag control information (TCI) field is used to represent a second portion of the service VLAN identifier. The first and second portions are then combined to obtain the service VLAN identifier of the packets completely.Type: GrantFiled: June 28, 2006Date of Patent: August 3, 2010Assignee: VIA Technologies Inc.Inventors: Yun-Fei Chao, Wei-Pin Chen
-
Patent number: 7767492Abstract: A multi-core/multi-package bus termination apparatus includes a first node, a location array, and a plurality of drivers. The first node receives a signal indicating whether a package upon which the processor core is disposed is internal to the bus or at a far end of the bus. The location array generates location signals indicating locations on the bus of nodes, where the locations are either an internal location or a bus end location. The drivers control how the nodes are driven. Each drivers has location-based multi-core/multi-package logic. The location-based multi-core/multi-package logic enables pull-up logic and first pull-down logic responsive to states of the first node ad the location signals.Type: GrantFiled: April 14, 2009Date of Patent: August 3, 2010Assignee: VIA Technologies, Inc.Inventors: Darius D. Gaskins, James R. Lundberg
-
Patent number: 7768512Abstract: A system and method for rendering a graphic primitive by linear or perspective interpolation from vertex points. An interpolation engine is employed to interpolate channel values along edges of the primitive to determine values along a scan line containing a selected point. The interpolation engine is then employed to interpolate along the scan line. Processing time may further be reduced by the use of an improved adder/subtractor as a component of the interpolation engine to reduce sequential steps and improve parallelism.Type: GrantFiled: August 10, 1999Date of Patent: August 3, 2010Assignee: Via Technologies, Inc.Inventors: Konstantine I. Iourcha, Chung-Kuang Chin, Zhou Hong
-
Patent number: 7770042Abstract: A microprocessor includes core logic that operates according to a core clock signal in order to execute program instructions, clock generation circuitry controllable to generate the core clock signal having one of N different possible frequencies, wherein N is more than two, and a control circuit. The control circuit, in response to a request to operate the core logic at a destination frequency, iteratively controls the clock generation circuitry to generate the core clock signal having a new frequency until the core clock signal frequency is the destination frequency. The new core clock signal frequency on each iteration is one of the N different possible frequencies monotonically closer to the destination frequency. The number of iterations is between zero and N?1 depending upon the destination frequency specified and the core clock signal frequency when the request is received.Type: GrantFiled: June 11, 2007Date of Patent: August 3, 2010Assignee: VIA Technologies, Inc.Inventor: Darius D. Gaskins
-
Patent number: 7764728Abstract: An apparatus for determining multipath correlations among a search range of input data, and a method thereof. The multipath searcher comprises a pseudo noise (PN) code generator, a correlator, and a data combiner. The PN code generator generates a first PN code corresponding to a first multipath component of the input data, postpones a first period based on the search range, then generates a second PN code corresponding to a second multipath component of the input data. The correlator is coupled to the PN code generator, and correlates the input data with the first PN code and the second PN code to produce a first correlation and a second correlation. The data combiner is coupled to the correlator, receives the first and the second correlations to determine a primary multipath component with a higher correlation thereto.Type: GrantFiled: October 18, 2006Date of Patent: July 27, 2010Assignee: Via Technologies, Inc.Inventors: Sung-Chiao Li, Huoy Bing Lim, Ching-Chia Hsu, Yu-Lin Wang
-
Patent number: 7760840Abstract: A clock-signal adjusting method and device is used for adjusting a frequency of a clock signal according to a frequency of an input data. The input data is sampled with a sampling frequency m times of the clock frequency to obtain a data transition waveform indicating data transition timing distribution. A unitary bit time of the input data is divided into m zones. A frequency relationship between the clock signal and the input data is determined according to a shift of the data transition waveform relative to the zones. The frequency of the clock signal is adjusted according to the frequency relationship.Type: GrantFiled: August 15, 2006Date of Patent: July 20, 2010Assignee: Via Technologies, Inc.Inventor: Chi Chang
-
Patent number: 7759905Abstract: A linear battery chargers is disclosed which comprises a current generator, a current detector, an operational amplifier, and a multiplexing device. The current generator provides current to charge a battery module, and the current is detected and transformed to a detected voltage by the current detector. The operational amplifier has an output terminal coupled to a control terminal of the current generator. In a constant current charge mode, the multiplexing device couples a first reference voltage and the detected voltage to first and second input terminals of the operational amplifier, respectively. The current generated by the current generator is maintained at a constant current level. In a constant voltage charge mode, the multiplexing device couples a second reference voltage and the voltage level of the battery module to the first and second input terminals of the operational amplifier, respectively. The voltage level of the battery module gradually approaches a constant voltage level.Type: GrantFiled: June 6, 2007Date of Patent: July 20, 2010Assignee: Via Technologies, Inc.Inventor: Chih-Min Liu
-
Patent number: 7760749Abstract: The invention provides an Ethernet physical layer (PHY) receiver. Ethernet PHY signals are simultaneously transmitted through first, second, third, and fourth duplex channels. The Ethernet physical layer receiver comprises a deskew first-in first-out (FIFO) module and a deskew control module. The deskew FIFO module includes four deskew FIFO buffers for respectively holding the Ethernet PHY signals of the duplex channels, wherein the Ethernet PHY signals of the duplex channels are respectively retrieved from the deskew FIFO buffers for further processing through read points of the deskew FIFO buffers.Type: GrantFiled: January 11, 2007Date of Patent: July 20, 2010Assignee: Via Technologies, Inc.Inventors: Chih-Chi Wang, Yi-Hua Lai