Abstract: A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep.

Abstract: A circuit substrate includes a circuit stack, a patterned conductive layer, a dielectric layer, and a plurality of thickening conductive layers. The circuit stack has a surface. The patterned conductive layer is located on the surface of the circuit stack and has a plurality of traces. Each of the traces has a bonding segment. The dielectric layer is located on the surface of the circuit stack and covers the patterned conductive layer. Besides, the dielectric layer has a plurality of bonding openings. Each of the bonding openings exposes the corresponding bonding segment. Each of the thickening conductive layers is located on the corresponding bonding segment. A semiconductor package structure having the above circuit substrate and a process for fabricating a circuit substrate are also provided.

Abstract: A semiconductor device includes an insulating layer disposed over a substrate, wherein the insulating layer has a center region. A first winding portion and a second winding portion are electrically connected to the first winding portion, disposed in a first level of the insulating layer and surrounding the center region, wherein each of the first winding portion and the second winding portion comprises a plurality of conductive lines arranged from the inside to the outside. A first extending conductive line and a second extending conductive line partially surround the first extending conductive line, and are disposed in the first level of the insulating layer, wherein the first winding portion and the second winding portion surround the first extending conductive line and the second extending conductive line. A third extending conductive line is disposed in a second level of the insulating layer and surrounding the center region.

Abstract: An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of an APIC access.

Abstract: EMarker and associated cable and method. The cable includes a CC (configuration channel) wire, the eMarker includes an active trigger circuit and a protection circuit coupled to the active trigger circuit and the CC wire. When a second port connects a first port via the cable, if a predefined event happens, the active trigger circuit triggers the protection circuit to change an electric characteristic of the CC wire, such that the first port detects a detachment of the second port.

Abstract: An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of a change in system state.

Abstract: A sorting method of data documents is provided, adapted to an electronic device. The sort method includes the following steps: retrieving a plurality of keywords from contents of a plurality of data documents; retrieving a keyword ranking corresponding to the at least one first keyword by a search engine; searching a keyword category corresponding to the at least one first keyword; and inputting the at least one first keyword, the keyword ranking and the keyword category of each of the at least one first keyword into a sort algorithm thereby outputting a predicting ranking of the first data document to sort the first data document, wherein the sort algorithm is generated based on contents of a plurality of second data documents and a current ranking of each of the plurality of second data documents.

Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.

Abstract: A non-volatile memory (NVM) apparatus and a data de-duplication method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller performs an error checking and correcting (ECC) method to convert a raw data into an encoded data. The controller performs the data de-duplication method to reduce a number of times that the same encoded data is repeatedly written into the NVM. The controller generates the feature information corresponding to the raw data by reusing the ECC method. When the feature information is found in a feature list, the encoded data corresponding to the raw data will not be written into the NVM. When the feature information is not found in the feature list, the feature information is added into the feature list, and the encoded data corresponding to the raw data is written into the NVM.

Abstract: A display method and a display system for a video wall are proposed. The method is applicable to a display system having a server and multiple player devices. Each of the player devices is connected to the server and a video wall having multiple displays, and each of the player devices corresponds to a different one of the displays and a different one of regions in a video stream. The method includes to receive the video stream from the server by each of the player devices, to send a broadcast command by a master player device among the player devices to other player devices, and to start displaying the corresponding region in a first frame of the video stream on the corresponding display of the video wall by each of the player devices after a preset delay time interval according to the broadcast command.

Abstract: A method is provided that compensates for misalignment on a synchronous data bus.

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a first signal, and is configured to generate a second signal, where the replica radial distribution element comprises replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time. The bit lag control element has delay lock control and a gray encoder.

Abstract: A voice control method, a mobile terminal device, and a voice control system are provided. The voice control method includes the following steps. An application provides at least one operating parameter for a speech software development module. The speech software development module receives a voice signal and parses the voice signal, and thus a voice recognition result is obtained. The speech software development module determines whether the voice recognition result matches the operating parameters. When the voice recognition result matches the operating parameters, the speech software development module provides an operating signal for the application.

Abstract: A USB chipset coupled between a first device and a second device is provided. A data processing unit is coupled to the first device and generates a plurality of transmission information according to first information provided by the first device. A transmitting unit is coupled to the data processing unit to transmit the transmission information to the second device and includes a converting module, a first output driving module, a second output driving module, and a transmitting-terminal selecting module. The converting module is coupled to the data processing unit to receive the transmission information in parallel and serially outputs the transmission information. The first output driving module is coupled to a first pin set. The second output driving module is coupled to a second pin set. The transmitting-terminal selecting module is coupled between the converting module and the first and second output driving modules.

Abstract: A controller device and an operation method for a non-volatile memory with 3-dimensional architecture are provided. The controller device includes an error checking and correcting (ECC) circuit and a controller. The controller is coupled to the non-volatile memory and the ECC circuit. The controller may access a target wordline of the non-volatile memory in accordance with a physical address. The controller groups a plurality of wordlines of the non-volatile memory into a plurality of wordline groups, wherein different wordline groups have different codeword structures. The controller controls the ECC circuit according to the codeword structure of the wordline group of the target wordline, and the ECC circuit generates a codeword to be stored in the target wordline or check a codeword from the target wordline under control of the controller.

Abstract: An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of a power glitch exceeding a specified threshold within a specified time period.

Abstract: An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of a fuse array access.

Abstract: The LDPC apparatus includes an LDPC iteration calculating circuit, a decision-bit storage circuit, and a convergence detection circuit. The LDPC iteration calculating circuit performs an LDPC iteration calculation to obtain a new decision bit value of a corresponding variable node. The decision-bit storage circuit uses the new decision bit value to update one corresponding old decision bit value among a plurality of old decision bit values. The convergence detection circuit stores check sums of a plurality of check nodes. The convergence detection circuit uses the new decision bit value and the corresponding old decision bit value to update one corresponding check sum among the check sums. The convergence detection circuit determines whether the LDPC iteration calculation is converged based on the check sums of the check nodes.

Abstract: A non-volatile memory device including a non-volatile memory and a controller is provided. The controller establishes a standard table and at least one priority table according to a read table stored in the non-volatile memory. The probability that the controller utilizes the read voltages corresponding to the indexes recorded in the priority table to read and successfully decode the codewords stored in non-volatile memory is high. When the controller utilizes the read voltages corresponding to the indexes recorded in the priority table to read and unsuccessfully decode the codewords, the controller utilizes the read voltages corresponding to the indexes recorded in the standard table to read and decode the codewords stored in non-volatile memory.

Abstract: A method for displaying landmark data from a search of a place name keyword, the method includes: inputting the place name keyword to a server to search for a plurality of landmark data, wherein each of the landmark data comprises fields of a landmark name, an objective level category, an address, and an address quoting frequency; sorting the landmark data by an electronic device to a display order, based on a characterized parameter for each of the landmark, wherein the characterized parameter is calculated based on at least a publicity, wherein the publicity is a calculation of the objective level category and the address quoting frequency with respectively weighting to the objective level category and the address quoting frequency; and displaying the landmark data by the electronic device according to the display order.