Abstract: A transmission circuit including an equalizer circuit, a slicer circuit, a signal detection circuit, and a control circuit is provided. The equalizer circuit performs an equalizing operation on an input signal according to preset states to output an equalizing signal corresponding to each preset state. The slicer circuit performs a slicing operation on the equalizing signal to output a slicing signal. The signal detection circuit detects and compares the equalizing signal and the slicing signal and accordingly adjusts the equalizer circuit to one of the preset states. The control circuit receives the slicing signal corresponding to each preset state, compares the slicing signal corresponding to each preset state with a plurality of signal patterns to generate a comparison result, and selects one of the preset states according to the comparison result, such that the control circuit let the equalizer circuit perform the equalizing operation according to the selected preset state.

Abstract: A circuit layout structure is suitable for a circuit board and includes following components. A first differential pair and a second differential pair respectively extend from the inside of a chip area of the circuit board to the outside of the chip area through a first patterned conductive layer of the circuit board, and respectively extend between the chip area and a port area of the circuit board through a second patterned conductive layer of the circuit board. A third differential pair extends from the chip area to the port area through the first patterned conductive layer. A first ground plane is constituted by the first patterned conductive layer. Orthogonal projections of the first differential pair and the second differential pair on the second patterned conductive layer overlap the first ground plane.

Abstract: An apparatus includes a fuse array, a stores, and a plurality of cores. The fuse array is programmed with compressed configuration data. The stores is for storage and access of decompressed configuration data sets. One of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store the decompressed configuration data sets for one or more cache memories in the stores. Each of the plurality of cores includes reset logic and sleep logic. The reset logic is configured to employ the decompressed configuration data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic is configured to determine that power is restored following a power gating event, and is configured to subsequently access the stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following the power gating event.

Abstract: An apparatus includes a fuse array and a stores. The fuse array is programmed with compressed configuration data for a plurality of cores. The stores is coupled to the plurality of cores, and includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores accesses the semiconductor fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores. Each of the plurality of cores has sleep logic. The sleep logic is configured to subsequently access a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following a power gating event.

Abstract: A method and system for controlling multiple displays is provided. The disclosed method is used to control a plurality of graphics processing units (GPUs), wherein every GPU controls one or more displays. The method includes the following steps: providing a graphical interface the same to a graphical program library of an operating system to replace the graphical program library to receive a drawing command from an application program; determining a display set of the GPUs according to a display region of the application program, wherein a frame displayed by the display controlled by each GPU is intersected to the display region; and delivering coordinate-transformed drawing commands to the GPUs in the display set according to the display intersection region, wherein each GPU in the display set only draws the content of the corresponding display intersection region.

Abstract: A voice control device and a corresponding voice control method are provided. The voice control device includes a sound receiver, a sound converter, a voice identifier, and a central processing unit (CPU). The sound receiver receives a first sound signal. The sound converter converts the first sound signal from analog signal to digital signal. The voice identifier identifies a first voice signal from the first sound signal, performs a first comparison on the first voice signal and a second voice signal, and generates a wake-up signal according to the first comparison. When receiving the wake-up signal, the CPU enters a working state from a sleeping state, performs a second comparison on the first voice signal and the second voice signal, and takes over the voice input from the sound receiver and the sound converter according to the second comparison.

Abstract: A graphics processing unit (GPU) and a management method of the GPU are provided. The GPU includes at least one graphics engine and an engine manager. The graphics engine performs a video decoding function or a graphics rendering function according to a graphics command from a driver software. The engine manager records a workload index of each graphics engine. The engine manager also adjusts the work ability of one of or more of the at least one graphics engine according to an adjustment command from the driver software. The driver software provides the adjustment command according to the workload index.

Abstract: A system and a method for assigning virtual functions, and a management host thereof are provided. The management host is connected with a computer host through a bridge and has at least one virtual function. A management processor of the management host updates a mapping table according to a virtual function establishing request to assign the at least one virtual function to the computer host according to the mapping table, wherein the management processor determines whether to establish the virtual function according to the mapping table. The management processor transmits a hot-plug event to the corresponding computer host via a switch according to an assignment result and connects the virtual function with the corresponding computer host to dynamically adjust an allocation of the virtual function.

Abstract: A memory controller is provided. The memory controller includes a memory interface and an encoding module. The memory interface is configured to couple to a memory chip. The encoding module is coupled to the memory interface and includes a shared memory and a parity generation module. The parity generation module is coupled to the shared memory. The parity generation module reads at least one basic vector from the shared memory, determines a dimension of the at least one basic vector, generates a generation matrix according to the at least one basic vector, converts a raw data into a codeword through the generation matrix, and stores the codeword into the memory chip through the memory interface.

Abstract: A method of fabricating a circuit board includes the following steps. A first and a second patterned conductive layer are plated on the first and the second surface of a core substrate, respectively. A first and a second extending pad are individually plated on a first and a second pad of the first and the second patterned conductive layer, respectively. A first and a second thermal-curing type dielectric layer are individually formed on the first and the second surface to cover the first and the second patterned conductive layer and the first and the second extending pad, respectively. A portion of the first and the second thermal-curing type dielectric layer respectively covering the top of the first and the second extending pad are removed. A protective film covers the second extending pad. The extending pad is removed by an etching process.

Abstract: A de-noise circuit and a de-noise method for differential signals and a chip for receiving differential signals are provided. The de-noise circuit includes a filter and a register. Both the filter and the register are disposed in the chip. The chip receives a differential signal through a first input terminal and a second input terminal. The filter is coupled between the first input terminal and the second input terminal of the chip. The filter filters out noises in the differential signal. The filter includes at least one filter unit. Each filter unit has at least one resistance value or at least one capacitance value. The register is coupled to the filter. The register receives and stores a control value. The register controls the resistance value or the capacitance value of at least one of the filter units based on the control value.

Abstract: A method and a playback control device are provided. The method, performed by the playback control device, includes: receiving a first request to playback a first data of a first wireless multimedia data type having a first priority; and playing back the first data if no other data of a wireless multimedia data type having a priority higher than the first priority is received.

Abstract: A three-dimensional (3D) graphics clipping method, a 3D graphics displaying method, and a 3D graphics processing apparatus using the same are provided. The 3D graphics clipping method includes following steps. A plurality of vertexes of a triangle is obtained, wherein a 3D object is constructed by using a plane of the triangle. Whether a view point is located between a first near clipping plane and a far clipping plane is determined. A second near clipping plane is set according to the determination result, and a view field is set between the second near clipping plane and the far clipping plane. A near clipping procedure is executed on the triangle according to the second near clipping plane. In the 3D graphics clipping method, a correct view field is determined in advance so that a graphics processing procedure is efficiently sped up and the accuracy of the near clipping procedure is increased.

Abstract: A microprocessor having performs an architectural instruction that instructs it to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if its architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result. To execute the second microinstruction, it writes the destination register with the result generated by the first microinstruction if the architectural condition flags satisfy the condition, and writes the destination register with the current value of the destination register if the architectural condition flags do not satisfy the condition.

Abstract: A hardware data prefetcher includes a queue of indexed storage elements into which are queued strides associated with a stream of temporally adjacent load requests. Each stride is a difference between cache line offsets of memory addresses of respective adjacent load requests. Hardware logic calculates a current stride between a current load request and a newest previous load request. The hardware logic compares the current stride and a stride M in the queue and compares the newest of the queued strides with a queued stride M+1, which is older than and adjacent to stride M. When the comparisons match, the hardware logic prefetches a cache line whose offset is the sum of the offset of the current load request and a stride M?1. Stride M?1 is newer than and adjacent to stride M in the queue.

Abstract: A data distributing and accessing method for sharing a file via a network system includes steps of: dividing the file into a plurality of blocks; distributing the blocks in a plurality of data hosts interconnected via the network system; one of the data hosts receiving a file-reading request from a user host and issuing collecting requests to other data hosts to collect the blocks from the data hosts; and transferring the collected blocks from the data hosts to the user host to be combined into the file.

Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.

Abstract: An embodiment of the invention provides a rechargeable battery module including a battery bank having serial connected battery units, a charging transistor providing a charging current to the battery bank, a balancing circuit for detecting and balancing voltage values of battery units and battery bank and a control chip. When a first voltage value of a first battery unit reaches a charge-off voltage, the control chip estimates a first unbalanced voltage difference between the first voltage and the minimal voltage among battery units. The control chip disables the charging transistor and estimates a second unbalanced voltage difference between voltages of the first battery unit and the battery unit having a minimal voltage. The control chip enables the balancing circuit to balance the first battery unit. When the voltage of the first battery is dropped by a calibration target, the charging transistor is enabled.

Abstract: An output buffer is provided. The output buffer is coupled to a first voltage source providing a first supply voltage and used for generating an output signal at an output terminal according to an input signal. The output buffer includes first and second transistors and a self-bias circuit. The first and second transistors are cascaded between the output terminal and a reference voltage. The self-bias circuit is coupled to the output terminal and the control electrode of the first transistor. When the output buffer does not receive the first supply voltage, the self-bias circuit provides a first bias voltage to the control electrode of the first transistor according to the output signal to decrease voltage differences between the control electrode and the input and output electrodes of the first transistor to be lower than a predetermined voltage.

Abstract: A Z culling method, a three-dimensional graphics processing method using Z-culling, and an apparatus thereof are provided. The Z-culling method includes the following steps. A Z cache memory is provided to buffer a cover mask and a dynamic maximum depth value corresponding to each tile. A draw mask, a draw maximum depth value, and a draw minimum depth value calculated according to the tile and a drawn part are obtained. Moreover, whether the drawn part is completely included in a known part of the cover mask is judged, and coordinated with a comparison of the draw minimum depth value and the dynamic maximum depth value, so as to determine whether to discard the drawn part and whether to update the cover mask and the dynamic maximum depth value in the Z cache memory. Accordingly, the bandwidth taken up in the system memory is reduced efficiently.