Patents Assigned to VIA Technologies
  • Patent number: 10216250
    Abstract: A memory apparatus and an energy-saving control method thereof are provided. The memory apparatus includes a plurality of non-volatile memory units and a control chip, and the control chip includes a specific circuit group, a memory control unit and an energy-saving control unit. The memory control unit controls an access to the non-volatile memory units. In a normal mode and during a period of accessing the non-volatile memory units by the control chip, if the non-volatile memory units are in a busy state, the energy-saving control unit controls the clock generation unit to stop outputting an internal clock signal to the specific circuit group, so as to reduce power consumption of the control chip.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: February 26, 2019
    Assignee: VIA Technologies, Inc.
    Inventors: Yi-Lin Lai, Chen-Te Chen
  • Patent number: 10218127
    Abstract: A paddle card includes a circuit board, a pad group and first to fourth shielding planes. The circuit board has an upper surface and a lower surface opposite to each other. The pad group is adapted to connect wires of a cable or terminals of a plug, and includes a pair of upper differential pads on the upper surface and a pair of lower differential pads on the lower surface. The pair of upper differential pads is respectively configured corresponding to the pair of lower differential pads in an up and down manner. The first to fourth shielding planes are stacked at intervals between the upper and lower surfaces in sequence. An orthogonal projection of a second opening of the second shielding plane on a geometric plane that a pair of third openings of the third shielding plane is located in is separate from the pair of third openings.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: February 26, 2019
    Assignee: VIA Technologies, Inc.
    Inventor: Sheng-Yuan Lee
  • Publication number: 20190057487
    Abstract: A method and an apparatus for generating 3D panoramic video are provided. In the method, plural frames are captured from a panoramic video. Each frame is transformed into a polyhedral mapping projection comprising side planes, a top plane and a bottom plane. Displacements of pixels in the side planes are calculated by using the side planes of each frame, and displacements of pixels in the top plane and the bottom plane are calculated by using the displacements of the side planes. Then, the pixels in the side planes, the top plane and the bottom plane of each frame are shifted according the displacements of the polyhedral mapping projection to generate a shifted polyhedral mapping projection. The shifted polyhedral mapping projection is transformed into a shifted frame with 2D space format. The shifted frames and corresponding frames construct 3D images and the 3D images are encoded into a 3D panoramic video.
    Type: Application
    Filed: June 13, 2018
    Publication date: February 21, 2019
    Applicant: VIA Technologies, Inc.
    Inventor: Robin J. Cheng
  • Patent number: 10184956
    Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: January 22, 2019
    Assignee: VIA Technologies, Inc.
    Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
  • Publication number: 20190006302
    Abstract: A process for fabricating a circuit substrate is provided. A dielectric layer is formed to cover a surface of a circuit stack and a patterned conductive layer, and has bonding openings exposing bonding segments of traces of the patterned conductive layer, and has plating openings exposing plating segments of the traces. A plating seed layer is formed to cover the surface of the circuit stack, the bonding segments, the plating segments, and the dielectric layer. A mask is formed to cover the plating layer and has mask openings exposing portions of the plating seed layer on the bonding segments. Portions of the plating seed layer on the bonding segments are removed with use of the mask as an etching mask. A thickening conductive layer is plated on each of the bonding segments with use of the mask as a plating mask. The mask and the plating seed layer are removed.
    Type: Application
    Filed: September 5, 2018
    Publication date: January 3, 2019
    Applicant: VIA Technologies, Inc.
    Inventor: Chen-Yueh Kung
  • Patent number: 10141953
    Abstract: A low-density parity-check (LDPC) apparatus and a matrix trapping set breaking method are provided. The LDPC apparatus includes a logarithm likelihood ratio (LLR) mapping circuit, a variable node (VN) calculation circuit, an adjustment circuit, a check nodes (CN) calculation circuit and a controller. The LLR mapping circuit converts an original codeword into a LLR vector. The VN calculation circuit calculates original V2C information by using the LLR vector and C2V information. The adjustment circuit adjusts the original V2C information to get adjusted V2C information in accordance with a factor. The CN calculation circuit calculates the C2V information by using the adjusted V2C information, and provides the C2V information to the VN calculation circuit. The controller determines whether to adjust the factor. When LDPC iteration operation falls into matrix trap set, the controller decides to adjust the factor so that the iteration operation breaks away from the matrix trap set.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: November 27, 2018
    Assignee: VIA Technologies, Inc.
    Inventors: Ying Yu Tai, Jiangli Zhu
  • Publication number: 20180329776
    Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a main buffer circuit, a multiplexer, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The main buffer circuit is coupled to the ECC decoding circuit for receiving and storing a first data portion of the decoded codeword. The multiplexer's first input end is coupled to the output end of the main buffer circuit. The second input end of the multiplexer is coupled to the output end of the ECC decoding circuit. The interface circuit is coupled to the output end of the multiplexer and receives the first data portion from the multiplexer to provide the first data portion to a host.
    Type: Application
    Filed: July 27, 2017
    Publication date: November 15, 2018
    Applicant: VIA Technologies, Inc.
    Inventors: Yi-Lin Lai, Chen-Te Chen, Ying-Che Chung
  • Patent number: 10119995
    Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: November 6, 2018
    Assignee: VIA Technologies, Inc.
    Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
  • Publication number: 20180314483
    Abstract: A system, a control apparatus and a control method for distributed video display are provided. The system includes an image source device configured to provide image data, a plurality of displays, a plurality of display chips respectively coupled to the displays and connected with the video source device through a network, and a control apparatus connected with the image source device and the display chips through the network and configured to transmit a playback signal to each of the display chips to control the display chips to receive the image data from the image source device and convert the received image data into display frames capable of being played by the displays.
    Type: Application
    Filed: July 19, 2017
    Publication date: November 1, 2018
    Applicant: VIA Technologies, Inc.
    Inventor: Steve Shu Liu
  • Patent number: 10108366
    Abstract: A non-volatile memory apparatus including a non-volatile storage circuit, a main memory and a controller, and an operating method thereof are provided. Each of a plurality of logical block address groups includes a plurality of logical block addresses. Each of the logical block address groups is assigned a group read-count value. An adjustment of the group read-count values is triggered by a read command of a host. When one read-count value of the group read-count values exceeds a preset range, the controller performs a scan operation to non-volatile storage blocks of the non-volatile storage circuit corresponding to a corresponding logical block address group of the read-count value, so as to check a number of error bits. The controller decides whether to perform a storage block data-moving operation to the non-volatile storage block corresponding to the corresponding logical block address group based on results of the scan operation.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: October 23, 2018
    Assignee: VIA Technologies, Inc.
    Inventors: Sheng-Huei Huang, Yi-Lin Lai
  • Patent number: 10103115
    Abstract: A circuit substrate includes a circuit stack, a patterned conductive layer, a dielectric layer, and a plurality of thickening conductive layers. The circuit stack has a surface. The patterned conductive layer is located on the surface of the circuit stack and has a plurality of traces. Each of the traces has a bonding segment. The dielectric layer is located on the surface of the circuit stack and covers the patterned conductive layer. Besides, the dielectric layer has a plurality of bonding openings. Each of the bonding openings exposes the corresponding bonding segment. Each of the thickening conductive layers is located on the corresponding bonding segment. A semiconductor package structure having the above circuit substrate and a process for fabricating a circuit substrate are also provided.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: October 16, 2018
    Assignee: VIA Technologies, Inc.
    Inventor: Chen-Yueh Kung
  • Publication number: 20180287366
    Abstract: EMarker and associated cable and method. The cable includes a CC (configuration channel) wire, the eMarker includes an active trigger circuit and a protection circuit coupled to the active trigger circuit and the CC wire. When a second port connects a first port via the cable, if a predefined event happens, the active trigger circuit triggers the protection circuit to change an electric characteristic of the CC wire, such that the first port detects a detachment of the second port.
    Type: Application
    Filed: January 11, 2018
    Publication date: October 4, 2018
    Applicant: VIA Technologies, Inc.
    Inventors: Cheng-Chun YEH, Wei-Hang LIN, Yu-Lung LIN, Feng-Kuan SU
  • Patent number: 10083241
    Abstract: A sorting method of data documents is provided, adapted to an electronic device. The sort method includes the following steps: retrieving a plurality of keywords from contents of a plurality of data documents; retrieving a keyword ranking corresponding to the at least one first keyword by a search engine; searching a keyword category corresponding to the at least one first keyword; and inputting the at least one first keyword, the keyword ranking and the keyword category of each of the at least one first keyword into a sort algorithm thereby outputting a predicting ranking of the first data document to sort the first data document, wherein the sort algorithm is generated based on contents of a plurality of second data documents and a current ranking of each of the plurality of second data documents.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: September 25, 2018
    Assignee: VIA Technologies, Inc.
    Inventors: Guo-Feng Zhang, Yi-Fei Zhu
  • Publication number: 20180267733
    Abstract: A non-volatile memory (NVM) apparatus and a data de-duplication method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller performs an error checking and correcting (ECC) method to convert a raw data into an encoded data. The controller performs the data de-duplication method to reduce a number of times that the same encoded data is repeatedly written into the NVM. The controller generates the feature information corresponding to the raw data by reusing the ECC method. When the feature information is found in a feature list, the encoded data corresponding to the raw data will not be written into the NVM. When the feature information is not found in the feature list, the feature information is added into the feature list, and the encoded data corresponding to the raw data is written into the NVM.
    Type: Application
    Filed: July 4, 2017
    Publication date: September 20, 2018
    Applicant: VIA Technologies, Inc.
    Inventors: Tingjun Xie, Ying Yu Tai, Jiangli Zhu
  • Publication number: 20180267084
    Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.
    Type: Application
    Filed: May 21, 2018
    Publication date: September 20, 2018
    Applicant: VIA Technologies, Inc.
    Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
  • Patent number: 10079963
    Abstract: A display method and a display system for a video wall are proposed. The method is applicable to a display system having a server and multiple player devices. Each of the player devices is connected to the server and a video wall having multiple displays, and each of the player devices corresponds to a different one of the displays and a different one of regions in a video stream. The method includes to receive the video stream from the server by each of the player devices, to send a broadcast command by a master player device among the player devices to other player devices, and to start displaying the corresponding region in a first frame of the video stream on the corresponding display of the video wall by each of the player devices after a preset delay time interval according to the broadcast command.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: September 18, 2018
    Assignee: VIA Technologies, Inc.
    Inventors: Steve Shu Liu, Chong Liu
  • Patent number: 10074365
    Abstract: A voice control method, a mobile terminal device, and a voice control system are provided. The voice control method includes the following steps. An application provides at least one operating parameter for a speech software development module. The speech software development module receives a voice signal and parses the voice signal, and thus a voice recognition result is obtained. The speech software development module determines whether the voice recognition result matches the operating parameters. When the voice recognition result matches the operating parameters, the speech software development module provides an operating signal for the application.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: September 11, 2018
    Assignee: VIA Technologies, Inc.
    Inventor: Guo-Feng Zhang
  • Patent number: 10055288
    Abstract: A controller device and an operation method for a non-volatile memory with 3-dimensional architecture are provided. The controller device includes an error checking and correcting (ECC) circuit and a controller. The controller is coupled to the non-volatile memory and the ECC circuit. The controller may access a target wordline of the non-volatile memory in accordance with a physical address. The controller groups a plurality of wordlines of the non-volatile memory into a plurality of wordline groups, wherein different wordline groups have different codeword structures. The controller controls the ECC circuit according to the codeword structure of the wordline group of the target wordline, and the ECC circuit generates a codeword to be stored in the target wordline or check a codeword from the target wordline under control of the controller.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: August 21, 2018
    Assignee: VIA Technologies, Inc.
    Inventors: Ying Yu Tai, Jiin Lai, Jiangli Zhu
  • Patent number: 10050643
    Abstract: The LDPC apparatus includes an LDPC iteration calculating circuit, a decision-bit storage circuit, and a convergence detection circuit. The LDPC iteration calculating circuit performs an LDPC iteration calculation to obtain a new decision bit value of a corresponding variable node. The decision-bit storage circuit uses the new decision bit value to update one corresponding old decision bit value among a plurality of old decision bit values. The convergence detection circuit stores check sums of a plurality of check nodes. The convergence detection circuit uses the new decision bit value and the corresponding old decision bit value to update one corresponding check sum among the check sums. The convergence detection circuit determines whether the LDPC iteration calculation is converged based on the check sums of the check nodes.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: August 14, 2018
    Assignee: VIA Technologies, Inc.
    Inventors: Ying Yu Tai, Jiangli Zhu
  • Publication number: 20180225305
    Abstract: A method for displaying landmark data from a search of a place name keyword, the method includes: inputting the place name keyword to a server to search for a plurality of landmark data, wherein each of the landmark data comprises fields of a landmark name, an objective level category, an address, and an address quoting frequency; sorting the landmark data by an electronic device to a display order, based on a characterized parameter for each of the landmark, wherein the characterized parameter is calculated based on at least a publicity, wherein the publicity is a calculation of the objective level category and the address quoting frequency with respectively weighting to the objective level category and the address quoting frequency; and displaying the landmark data by the electronic device according to the display order.
    Type: Application
    Filed: March 28, 2018
    Publication date: August 9, 2018
    Applicant: VIA Technologies, Inc.
    Inventors: Guo-Feng Zhang, Yi-Fei Zhu