Abstract: A method for vehicle blind zone detection, applied to an electronic device coupled to one or more cameras arranged on a vehicle, the method comprising: setting a capture zone in a current frame image captured by the camera and detecting an object entering the capture zone in the current frame image, wherein the object meeting a capture criterion and a location information of the object meeting the capture criterion are added into a tracking list; performing tracking operations on an existing object, which has been detected and thus added to the tracking list, in one or more previous frame images preceding the current frame image captured by the camera, to obtain a new location information of the existing object in the current frame image, and determining whether to have the existing object remained in the tracking list in accordance with the new location information of the existing object and the detection scope; and making a warning determination in accordance with the location information in the current fra

Abstract: A method, an apparatus and a system for displaying an image of a vehicle blind spot are provided. The apparatus is coupled to at least one external camera disposed outside the vehicle, at least one internal camera disposed inside the vehicle with a lens facing towards a driver, and at least one display disposed inside the vehicle. The method comprises capturing an image of the external environment of the vehicle by the external camera as an external image, capturing an image including the driver by the internal camera as an internal image, recognizing a face of the driver and a displacement of the face in the internal image, and adjusting a position of an ROI in the external image according to the recognized displacement, to display an image of the ROI on the display corresponding to the external camera. The displayed image of the external of the vehicle may be adjusted according to the posture or the angle of view of the driver, to have the image of the current blind spot by the driver shown correctly.

Abstract: An architecture of a multi-core electronic system is provided. The architecture includes a plurality of first computing cores, a first ring bus, a direct memory access (DMA) engine, and a DMA ring controller. The first computing cores are connected to the first ring bus. The DMA ring controller connects the DMA engine to the first ring bus. The first computing cores communicate with the DMA engine through the first ring bus and make the DMA engine perform a memory operation.

Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a first cyclic redundancy check (CRC) circuit, a second CRC circuit, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The interface circuit receives and provides a first data portion of the decoded codeword to a host. The first CRC circuit performs a first CRC on the first data portion and generates a check status message based on a relationship between a result of the first CRC and a first CRC code of the decoded codeword. The second CRC circuit performs a second CRC on the first data portion to generate a second CRC code. The second CRC circuit determines whether to further change the second CRC code to make the second CRC code not match the first data portion according to the check status message.

Abstract: A non-volatile memory (NVM) apparatus and an iteration sorting method thereof are provided. The NVM apparatus performs the iteration sorting method to select one target block from a plurality of blocks of a NVM, and to perform a management operation on the target block. The iteration sorting method includes: selecting a plurality of candidate blocks among the blocks of the NVM to join into a sorting set, sorting all of the candidate blocks in the sorting set according to metadata, picking one candidate block with maximum (or minimum) metadata from the sorting set to serve as the target block, and keeping M candidate blocks in the sorting set and discarding the rest of the candidate blocks from the sorting set.

Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a main buffer circuit, a multiplexer, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The main buffer circuit is coupled to the ECC decoding circuit for receiving and storing a first data portion of the decoded codeword. The multiplexer's first input end is coupled to the output end of the main buffer circuit. The second input end of the multiplexer is coupled to the output end of the ECC decoding circuit. The interface circuit is coupled to the output end of the multiplexer and receives the first data portion from the multiplexer to provide the first data portion to a host.

Abstract: A method for detecting conflicts between aircraft flying in controlled airspace. The method determines whether pairs of aircraft flight routes violate a predetermined proximity test. The separation of pairs of aircraft whose flight routes do not violate the proximity test is assured. For pairs of aircraft whose flight routes violate the proximity test, the method calculates the parts of their flight routes that breach the separation threshold, the conflict paths (406, 408). The conflict paths are stored. The method determines the portions of aircraft trajectories corresponding to the conflict paths. The separation of aircraft that have flown past their conflict paths is assured. The separation time and separation altitude of pairs of aircraft that have not flown past their conflict paths are calculated. The separation time and separation altitude are used to determine future circumstances whereby the pairs of aircraft may lose separation.

Abstract: A non-volatile memory (NVM) apparatus and an address classification method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller accesses the NVM in accordance with a write command of a host. The controller may perform the address classification method. The address classification method includes: providing a data look-up table, wherein the data look-up table includes a plurality of data entries, each of the data entries includes a logical address information, a counter value and a timer value; searching the data look-up table based on the logical address of the write command in order to obtain a corresponding counter value and a corresponding timer value; and determining whether the logical address of the write command is a hot data address based on the corresponding counter value and the corresponding timer value.

Abstract: The invention introduces a method for blocking unauthorized applications, at least containing: receiving an input parameter from an application; determining whether the application is authenticated by inspecting content of the input parameter; randomly generating a session key, storing the session key in a file and storing the file in a path that can be accessed by a motherboard support service and the application only when the application is authenticated; and replying with the path and a filename of the file to the application.

Abstract: An electronic apparatus and a method of extending peripheral devices are provided. The electronic apparatus includes: a controller; and a plurality of peripheral devices electrically connected to the controller, wherein the plurality of peripheral devices include a plurality of video graphics array display cards, wherein in an initialization phase of the electronic apparatus, the controller allocates input/output resources to a first portion of the video graphics array display cards and does not allocate the input/output resources to a second portion of the video graphics array display cards, wherein the first portion of the video graphics array display cards allocated with the input/output resources is used to display an image in the initialization phase.

Abstract: An energy regulation circuit including a first voltage regulator, a processor, a second voltage regulator, and a controller is provided. The first voltage regulator adjusts an input voltage to generate an adjustment voltage. The processor increases the adjustment voltage according to the input voltage to generate a boost voltage. An energy accumulator is charged according to the boost voltage. The second voltage regulator adjusts the boost voltage to generate an operation voltage. The controller operates according to the operation voltage.

Abstract: A method and an apparatus for generating 3D panoramic video are provided. In the method, plural frames are captured from a panoramic video. Each frame is transformed into a polyhedral mapping projection comprising side planes, a top plane and a bottom plane. Displacements of pixels in the side planes are calculated by using the side planes of each frame, and displacements of pixels in the top plane and the bottom plane are calculated by using the displacements of the side planes. Then, the pixels in the side planes, the top plane and the bottom plane of each frame are shifted according the displacements of the polyhedral mapping projection to generate a shifted polyhedral mapping projection. The shifted polyhedral mapping projection is transformed into a shifted frame with 2D space format. The shifted frames and corresponding frames construct 3D images and the 3D images are encoded into a 3D panoramic video.

Abstract: A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.

Abstract: A natural language recognizing apparatus including an input device, a processing device and a storage device is provided. The input device is configured to provide a natural language data. The storage device is configured to store a plurality of program modules. The program modules include a grammar analysis module. The processing device executes the grammar analysis module to analyze the natural language data through a formal grammar model, and generate a plurality of string data. When at least one of the string data conforms to a preset grammar condition, the processing device judges the at least one of the string data is an intention data, and the processing device outputs a corresponding response signal according to the intention data. In addition, a natural language recognizing method is also provided.

Abstract: A system, a control apparatus and a control method for distributed video display are provided. The system includes an image source device configured to provide image data, a plurality of displays, a plurality of display chips respectively coupled to the displays and connected with the video source device through a network, and a control apparatus connected with the image source device and the display chips through the network and configured to transmit a playback signal to each of the display chips to control the display chips to receive the image data from the image source device and convert the received image data into display frames capable of being played by the displays.

Abstract: An architecture of a multi-core electronic system is provided. The architecture includes a plurality of first computing cores, a first ring bus, a direct memory access (DMA) engine, and a DMA ring controller. The first computing cores are connected to the first ring bus. The DMA ring controller connects the DMA engine to the first ring bus. The first computing cores communicate with the DMA engine through the first ring bus and make the DMA engine perform a memory operation.

Abstract: An audio playing apparatus and an audio transmission circuit are provided. The audio playing apparatus includes a first audio connector, a second audio connector, a player, and an audio transmission circuit. The second audio connector has a different interface specification than an interface specification of the first audio connector. The audio transmission circuit is coupled to the first audio connector, the second audio connector and the player. The audio transmission circuit detects a power pin of the first audio connector and a power pin of the second audio connector to obtain a determination result, and selects one of the first audio connector and the second audio connector as a target connector according to the determination result, so as to transmit an audio signal associated with the target connector to the player.

Abstract: An audio playing apparatus and an audio transmission circuit are provided. The audio playing apparatus includes a first audio connector, a second audio connector, a player, and an audio transmission circuit. The second audio connector has a different interface specification than an interface specification of the first audio connector. The audio transmission circuit is coupled to the first audio connector, the second audio connector and the player. The audio transmission circuit detects a power pin of the first audio connector and a power pin of the second audio connector to obtain a determination result, and selects one of the first audio connector and the second audio connector as a target connector according to the determination result, so as to transmit an audio signal associated with the target connector to the player.