Abstract: A programmable n stage shift counter divider circuit includes a plurality of n flip-flops arranged in cascade from a first stage to an nth stage. The data inputs of each of the flip flops are coupled with the output of the next preceding stage through corresponding OR gates. A source of preload signals is coupled with the second inputs of the OR gates; and a combined trap detector and terminal count detector has inputs coupled with the outputs of the last n-1 stages of the shift counter circuit and an output coupled with the source of pre-load signals to operate it.

Abstract: The present invention provides a radio signal controller comprising: a memory device having a plurality of memory locations individually configured to store at least one radio signal level value; a memory controller operable to sequentially address the memory locations; and a signal generator operable to receive at least one radio signal level value and output a radio control signal responsive thereto. The present invention additionally provides for a radio communication device, radio communication system and method of controlling a radio.

Abstract: A system is delineated comprising, in combination, an integrated circuit having N internal masters coupled to a buried, internal bus, and register circuitry coupled to the buried, internal bus and having an output providing status data for each of the N internal masters. The output from the register circuitry is directly coupled to a processor for permitting the processor to monitor request and grant status for each internal master, thereby allowing the processor to keep track of which, if any, of the internal masters attempt to "hog" the internal, buried bus. Additionally, the processor can set enabling registers located in the register circuitry to one value for permitting properly operating internal masters to have access to the internal, buried bus, and to another value to disable one or more "hogging" internal masters from accessing the internal, buried bus. The system further includes N external devices coupled, on a one-to-one basis, to the N internal masters.

Abstract: An integrated circuit includes a memory array implemented with as few as two transistors, and four access lines per cell. The array includes row lines and bit lines, with the internally-arranged bit lines shared by two adjacent cells. According to one embodiment, each memory cell includes a first transistor-based circuit in a first cell that is arranged to store information received over a corresponding one of the bit lines, and a second transistor-based circuit in a second cell that is arranged to output information over the same corresponding bit line.

Abstract: A remote control has the ability to record the aural characteristics of a user's listening environment. Integral microphones receive the loudspeaker output providing feedback to the unit while the user makes adjustments to the audio/visual equipment. The remote control is programmable to control a plurality of different makes and arrangements of remote-operable ANV equipment. The sonic characteristics of the loudspeakers in combination with the room's acoustics are processed by the remote in the form of a "sound signature." This "sound signature" is remembered along with the corresponding physical settings of the A/V equipment's controls to provide the user with a selectable listening experience.

Abstract: A die-up configuration includes a rigid circuit board with electrically conductive plated-through holes formed therethrough and an integrated-circuit die mounted to the upper surface of which a flexible insulated tape layer is fixed to the upper surface of a rigid circuit board and which has a number of wire-bonding sites. Conductive vias or plated-through holes are provided for connecting the wire-bonding sites on the upper surface of the flexible insulated tape layer to the contact areas formed on the lower surface of the flexible insulated tape layer. Conductors are provided for connecting respective contact areas on the lower surface of the flexible insulated tape layer to solder balls on the bottom of the rigid circuit board.

Abstract: Methods of inspecting for mask-defined, feature dimensional conformity between multiple masks which are utilized in lithographic processing are described. In one embodiment, a first mask having a first reference artifact thereon is exposed to conditions effective to transfer the first reference artifact onto a coated substrate. A second mask having a second reference artifact thereon is exposed to conditions effective to transfer the second reference artifact onto the coated substrate. The first and second reference artifacts are inspected to ascertain whether the second reference artifact is within desirable dimensional tolerances relative to the first reference artifact. In a preferred embodiment, the first and second reference artifacts contain at least one feature which defines a critical dimension of a photolithographic process utilized to form the artifacts.

Abstract: The present invention provides digital integrated circuits, buffers, digital devices and methods for buffering data. One embodiment of the digital integrated circuit comprises: a data input configured to receive an input signal at a first voltage; a data output configured to output an output signal at a second voltage; a controller coupled with the data input and the controller being configured to generate an internal control signal and an external control signal responsive to the input signal; the controller having a first voltage regulator configured to maintain the external control signal above a threshold and a feedback voltage regulator configured to maintain the internal control signal above a threshold; and an output driver coupled with the data output and the controller, the output driver being configured to apply the output signal to the data output responsive to the external control signal.

Abstract: A hot docking system and method for managing and detecting hot docking of bus cards. The hot docking system detects the load impedance at the power pins of the bus connector to determine whether a card has been inserted. When insertion is detected, bus activity on the connector is ceased until the card is completely inserted which is indicated by signals present on card detect pins which are mechanically shorter that the bus signal pins and thereby provide this insertion signal after all other connections are complete. The power supply pins are mechanically longer than the bus signal pins thereby providing an early indication that a card has been inserted. On removal of the card, the card detect pins disconnect before the bus signal pins or the power supply pins, signaling the system to halt bus activity but maintain power on the connector until the card is completely removed.

Abstract: A method of adaptive sampling for accurate computer model building. The present invention is used in conjunction with a computer system to build models of responses, functions, and the like, that produce a given output for a given input(s). One embodiment in accordance with the present invention includes a computer system, software instructions, and a function to be modeled. The present embodiment directs the computer system to generate a set of equidistant data points for the function based on an input value. The present embodiment directs the computer to use a modeling curve to generate a set of prediction data points based on the odd positioned data points of the equidistant data points. The present embodiment directs the computer to determine whether the locations of the predicted data points satisfy a predetermined convergence criterion with respect to the determined locations of the even positioned data points of the equidistant data points.

Abstract: A gate region of a transistor is prepared for receiving a deposit of metal. A chemical mechanical polishing process is performed to reduce thickness of an insulation layer above the gate region. At the end of the chemical mechanical polishing process, a portion of the insulating layer remains above the gate region. An etch process is performed to remove the portion of the insulating layer remaining above the gate region. The etch process also removes a portion of polysilicon within the gate region and removes a top portion of spacers on either side of the gate region. A polysilicon selective etch-back is performed to remove an additional portion of the polysilicon within the gate region.

Abstract: A circuit arrangement, system, and method provide asynchronous control of a state logic circuit to facilitate testing of the state logic circuit. The state logic circuit includes stages selectively enabled by a clock signal that generate an output signal as a function of a history of a data signal. Upon application of a control signal, the alternate enabling circuit enables at least one of the stages regardless of the state of the clock signal, such that the output signal does not depend on the history of the data signal.

Abstract: A method and apparatus for a reinforced leadframe to substrate attachment in a semiconductor assembly. In one embodiment, a printed circuit board having a plurality of electrically coupled electrical contact regions and wire bond areas formed thereon has a leadframe attached thereto such that each of the bonding fingers of the leadframe is coupled to a respective electrical contact region on the printed circuit board. A ribbon of B-staged epoxy is disposed on the leadframe such that said leadframe is disposed between the ribbon of B-staged epoxy and the printed circuit board. An integrated-circuit die is mounted on the printed circuit board with the bonding fingers of the leadframe peripherally surrounding the integrated circuit die. The bonding pads on the integrated-circuit die are electrically coupled to respective wire bond areas on the printed circuit board.

Abstract: A semiconductor devices includes an anti-reflective structure for use in patterning metal layers in semiconductor devices. The anti-reflective structure is made, at least in part, using indium tin oxide. The anti-reflective structure is especially useful for patterning the metal layers with light having a wavelength of 190-300 nm. The anti-reflective structure may be a single indium tin oxide layer or may include a titanium nitride layer formed over the metal layer and an indium tin oxide layer formed over the titanium nitride layer. For many applications, the anti-reflective structure, in the presence of a photoresist layer, has a reflectivity of about 3% or less for light having a wavelength of 190-300 nm.

Abstract: A method of making an integrated circuit interconnect structure having air as the effective dielectric between metallization layers includes the steps of: a) providing an air dielectric formation layer of a sacrificial material over a substrate; b) forming a pillar holes in the air dielectric formation layer; c) filling the pillar holes with a non-sacrificial material; d) constructing a metallization layer over the sacrificial air dielectric formation layer and non-sacrificial material pillars; and e) applying an isotropic etchant to the interconnect structure to remove the sacrificial material, leaving the non-sacrificial material pillars for mechanical support of the metallization layer. An interconnect structure having an air dielectric includes a bottom metallization layer, a top metallization layer, and a plurality of pillars separating the bottom and top metallization layers and mechanically supporting the top metallization layer.

Abstract: The present invention provides methods and apparatus capable of efficiently combining a logic circuit die with a memory circuit die in a single integrated circuit device capable of supporting memory intensive applications, such as 3-dimensional graphics rendering, encryption and signal processing. The logic circuit die is produced independently with a logic circuit fabrication process that optimizes the logic circuit's performance and reduces costs, and the memory circuit die, which may contain a large memory circuit, can be produced independently with a memory circuit fabrication process that optimizes the memory circuit's performance and reduces costs. The circuit dies are attached directly together in a flip-chip fashion to create a unitary integrated circuit assembly having a high-performance, low impedance, wide-word interface.

Abstract: A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas. Specifically, one embodiment of the present invention utilizes a dry abrasive polishing pad to abrade the desired surface of the semiconductor wafer within a vacuum planarization chamber. As a result of abrading the surface, the abrasive polishing pad breaks the chemical bonds of a thin layer of the dielectric surface material.

Abstract: A damascene structure and method for forming such structure. In one embodiment, the damascene structure of the present invention includes a first layer of oxide which is a stochiometric oxide deposited onto a semiconductor substrate. A second layer of oxide which is a non-stochiometric oxide is then deposited onto the semiconductor substrate which is followed by a stochiometric oxide layer. The semiconductor substrate is then masked and etched so as to form vias using a selective etch process which etches the stochiometric oxide and stops etching on the non-stochiometric oxide layer. The etch chemistry is then changed in-situ, allowing the removal of the non-stochiometric oxide at the bottom of the via. The wafer is then re-masked in the pattern of trench interconnect using a selective etch process to selectively etch the layer of stochiometric oxide in the damascene trench down to the layer of non-stochiometric oxide while simultaneously completing the etching of vias.

Abstract: An arrangement for providing command responses in a sequence that is independent of the sequence that commands are initiated by an initiating bus to a target bus. A first memory array stores commands from the initiating bus in a first sequence, and provides the commands to the target bus in a first sequence. Multiple delayed completion registers are provided, each to receive and store one of the commands entered into the first memory array. The delayed completion registers re-enter its corresponding stored command into the first memory array when a request is received to reissue the command. A second memory array stores command responses in a second sequence that relates to the order that their corresponding commands were successfully completed on the target bus.

Abstract: Disclosed is a method for encapsulating a via over a first metal layer of a semiconductor substrate in a damascene processing to prevent voiding. The method includes forming an intermetal oxide (IMO) layer over the first metal layer and forming a via in the IMO layer such that the via exposes a portion of the first metal layer and a side wall of the via in the IMO layer. The method also includes conformally forming a first barrier layer over the IMO layer and the via such that a portion of the first barrier layer is deposited over the side wall of the IMO layer and the exposed portion of the first metal layer. The method further includes depositing a second metal layer over the first barrier layer such that the second metal layer fills the via within the first barrier layer portion deposited in the via to form a metal via.