Patents Assigned to VLSI Technology, Inc.
  • Patent number: 6170080
    Abstract: A method and a system implement a circuit design in an integrated chip. A floorplan of the circuit design is arranged at a high level of abstraction. The design is synthesized based on the floorplan, and the synthesized design is laid out physically on the integrated circuit.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: January 2, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Arnold Ginetti, Gerrard Tarroux, Francois Silve, Jean-Michel Fernandes, Philippe Troin, Jean-Charles Giomi
  • Patent number: 6167499
    Abstract: A technique for conserving digital memory space is disclosed. This technique includes sequentially transmitting a first address and a second address on a first bus coupled to a FIFO memory. The first address is stored in the memory and compared to the second address to determine a first value corresponding to a difference between the first and second addresses. This first value is written in the memory to represent the second address and has a bit size smaller than the second address. A method to decode the first value to regenerate the second address is also disclosed. These techniques may be further enhanced by only storing an address in a sequential access memory when it differs from the most recently stored address in the memory.
    Type: Grant
    Filed: May 20, 1997
    Date of Patent: December 26, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: Lawrence Letham
  • Patent number: 6165048
    Abstract: A chemical-mechanical-polishing system having a slurry distribution system, a polisher, a deionized water supply, and a drain, includes a slurry filtration system. The filtration system has two filters for alternately filtering particles in slurry and being backflushed with deionized water. Two input valves have input ports connected to the slurry distribution system and output ports respectively connected to the filters for filtering. Two output valves have input ports respectively connected to the filters for receiving filtered slurry and output ports connected to the polisher. Two backflush valves have input ports connected to the deionized water supply and output ports respectively connected to backflush with deionized water; the output ports are also respectively connected to the input ports of the two output valves. Two drain valves have input ports respectively connected to the filters for receiving backflushed fluid and output ports connected to the drain.
    Type: Grant
    Filed: November 10, 1998
    Date of Patent: December 26, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Richard D. Russ, Daniel Thomas
  • Patent number: 6166580
    Abstract: A voltage-buffer circuit for changing an input signal at a first voltage range to an output signal at a second voltage range. In one embodiment, the voltage-buffer circuit is comprised of an input lead for receiving an input signal at a first voltage range, a plurality of transistors coupled to the input lead, and an output lead coupled to the plurality of transistors. The purpose of the transistors is to convert the input signal at the first voltage range to an output signal at a second voltage range. The output lead is for receiving the output signal at the second voltage range from said plurality of transistors. The plurality of transistors are arranged into a plurality of stages, with at least one of the transistors having a gate oxide of a first thickness and at least one of the transistors having a gate oxide of a second thickness, where the first thickness is less than said second thickness.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: December 26, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: D. C. Sessions
  • Patent number: 6163058
    Abstract: The present invention includes differential devices and methods of protecting a semiconductor device. One aspect of the present invention provides a differential device adapted to be coupled to a ground connection, the differential device comprising: a first interconnect; a second interconnect; a common diffusion region; a first MOS device coupled with the common diffusion region and the first interconnect; a second MOS device coupled with the common diffusion region and the second interconnect; and a tail MOS device coupled with the common diffusion region and adapted to be coupled to a ground connection.
    Type: Grant
    Filed: September 24, 1999
    Date of Patent: December 19, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Jon R. Williamson, Derwin W. Mattos
  • Patent number: 6162650
    Abstract: A test device and method for determining parameters of a plurality of vias formed into a dielectric material making contact to a buried conductive layer. The present invention is comprised of a sample structure disposed within the material through which a plurality of vias are to be formed. The sample structure is adapted to enhance secondary electron yield from the via bottom during a scanning electron microscope examination of the vias. Additionally, the plurality of vias to be formed are disposed intentionally offset with respect to the sample structure. As a result, the enhanced secondary electron yield from the sample structure characterizes the degree of misalignment present in the via formation process. In so doing, the present invention simultaneously quantifies the critical dimension of the vias, the alignment/registration of the via formation process, and determines whether or not the vias are etched to a minimum desired depth.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: December 19, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Ian Robert Harvey, Satyendra Sethi
  • Patent number: 6159075
    Abstract: A method for optimizing CMP (chemical mechanical polishing) processing of semiconductor wafers on a CMP machine. The optimization method includes the steps of polishing a test series of semiconductor wafers on a CMP machine. During the CMP processing, a film thickness is measured at a first point proximate to the center of each respective wafer using a film thickness detector coupled to the machine. A film thickness at a second point proximate to the outside edge of the respective wafers is also measured. Based upon the in-process film thickness measurements at the first point and the second points, the optimization process determines a polishing profile describing a removal rate and a removal uniformity with respect to a set of process variables. The process variables include different CMP machine settings for the polishing process, such as the amount of down force applied to the wafer. The polishing profile is subsequently used to polish production wafers accordingly.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: December 12, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: Liming Zhang
  • Patent number: 6156588
    Abstract: The invention relates generally to integrated circuits and, in particular, to methods of forming anti-fuse structures during integrated circuit manufacture. In an exemplary embodiment of the invention, a conductive base layer is formed over a semiconductor substrate. An insulating layer is formed on the conductive base layer and is patterned to expose a portion of the conductive base layer. An anti-fuse layer is formed on the insulating layer and the exposed portion of the conductive base layer. A conductive protection layer is formed on the anti-fuse layer. An anti-fuse island is formed by sequentially removing a portion of the conductive protection layer, and underlying portions of the anti-fuse layer and the insulating layer. The conductive base layer is patterned after forming the anti-fuse island. The invention provides a simplified method for the formation of anti-fuse structures which is compatible with submicron device geometries.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: December 5, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Ivan Sanchez, Miguel A. Delgado
  • Patent number: 6153456
    Abstract: An integrated circuit is disclosed that includes a semiconductor substrate, an oxide layer on the substrate, and a polysilicon layer on the oxide layer. The polysilicon layer extends away from the substrate and is doped with elemental boron to increase electrical conductivity thereof. Boron difluoride atoms are implanted in the substrate to define corresponding source and drain regions. Initially, the boron difluoride ions also penetrate a portion of the polysilicon layer. At least a portion of the polysilicon layer is removed to substantially reduce the fluorine-induced migration of boron through the oxide layer to the substrate.
    Type: Grant
    Filed: January 14, 1998
    Date of Patent: November 28, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Xi-Wei Lin, Emmanual de Muizon
  • Patent number: 6154018
    Abstract: A high differential impedance load device. The present invention recites a load device including a first lead, a second lead, a first current mirror, a second current mirror, and a third lead. First lead, second lead, and third lead are coupled to first current mirror and second current mirror such that a current sunk on first lead is approximately equal to a current sunk on second lead. Third lead represents a reference voltage which is ground.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: November 28, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: D. C. Sessions
  • Patent number: 6154508
    Abstract: A clock synchronization circuit for synchronizing a first communications device and a second communications device to enable digital communication between the devices. The clock synchronization circuit includes an oscillator circuit adapted to generate a base clock signal. A first frequency divider is coupled to the oscillator circuit. The first frequency divider generates a first divider clock signal from the base clock signal. A phase comparison circuit is coupled to receive the first divider clock signal. Additionally, the phase comparison circuit is also coupled to the oscillator circuit to control the frequency of the base clock signal. The phase comparison circuit receives a reference clock signal from a first communications device and adjusts the base clock frequency to correct a phase difference between the first divider clock signal and the reference clock signal. The clock synchronization circuit further includes a second frequency divider coupled to the oscillator circuit.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: November 28, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: Stefan Ott
  • Patent number: 6154800
    Abstract: An apparatus for and a method of arbitrating a stream of access requests over multiple outputs. In one embodiment, the apparatus is implemented with D*[W+(N+1) log.sub.2 D] storage elements, where D is a maximum number of outstanding requests allowed by an issuing agent, N is a number of different request types, and W is a width of access requests measured in bits. The present embodiment comprises a main queue, an input address selection circuit coupled to the main queue for selecting storage locations to receive a stream of access requests, and a plurality of output address selection circuits coupled to the main queue for selecting storage locations to be read. Significantly, the input address selection circuit includes an input address list pointing to vacant storage locations in the main queue, and the input address list is updated each time an access request is stored in, or read out from, the main queue.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: November 28, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: Vishal Anand
  • Patent number: 6150234
    Abstract: An isolation structure on an integrated circuit is formed using a shallow trench isolation process. On a substrate, a trench is formed. A thermal anneal is performed to oxidize exposed areas of the substrate to provide for round corners at a perimeter of the trench. The thermal anneal in performed in an ambient where a chlorine source is added to O.sub.2 in order to minimize facets while creating the round corners. Oxidation time is lengthened by introducing an inert gas during the thermal anneal.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: November 21, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: Christopher S. Olsen
  • Patent number: 6150843
    Abstract: A 5 volt tolerant I/O buffer circuit is coupled to a power supply terminal of a predetermined power supply voltage, for driving an I/O pad to a logic state depending on an input signal and an output enable signal. The I/O buffer circuit minimizes current flow into the power supply terminal when the pad is coupled to a voltage greater than the predetermined power supply voltage. A driver transistor of a first type is formed within a diffusion well and is coupled to the predetermined power supply voltage and to the pad. First and second terminals of a protection transistor are coupled to respective ones of the predetermined power supply voltage and the diffusion well. Circuitry is provided for, when the output enable signal is active, turning on the protection transistor so as to couple the predetermined power supply voltage to the diffusion well, regardless of a voltage level of the pad. A single protection transistor is sufficient to prevent current leakage through the parasitic PN diode.
    Type: Grant
    Filed: January 29, 1998
    Date of Patent: November 21, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: James D. Shiffer, Waseem Ahmad
  • Patent number: 6150266
    Abstract: A local interconnect structure that includes a silicon spacer. After deposition of polysilicon gates and formation of spacers on a semiconductor substrate, photolithography and oxide etch steps are performed to remove a portion of a spacer along a segment of the gate where local interconnection is to be formed. A thin screen oxide layer is deposited over the wafer, followed by the formation of diffusion regions. A silicon layer (either amorphous or polycrystalline) is then deposited. The silicon layer is then selectively etched so as to form a silicon spacer along the segment of the gate where local interconnection is to be formed. A conventional SALICIDE process is performed, leading to simultaneous silicidation of the diffusion region, the gate, and the silicon spacer. The resulting local interconnect electrically connects the gate and the diffusion region.
    Type: Grant
    Filed: January 28, 1999
    Date of Patent: November 21, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Xi-Wei Lin, Emmanuel de Muizon
  • Patent number: 6147893
    Abstract: A method and apparatus for programmable read only memory with high speed differential sensing at low operating voltage. In one embodiment, a programmable memory cell is comprised of word line, a bitline, and a transistor. The transistor, representing a single binary digit (bit), has a gate coupled to a word line, a drain coupled to a bitline, and a source capable of being programmed to provide a logic level of 0 and a logic level of 1. By programming the source of the transistor, the bitline approximately equal capacitance for both logic level 0 and logic level 1 states.
    Type: Grant
    Filed: January 27, 1999
    Date of Patent: November 14, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: Kwo-Jen Liu
  • Patent number: 6148365
    Abstract: In accordance with the preferred embodiment of the present invention, a first-in-first out queue includes a buffer for storing data. A write pointer indicates a next position for data to be written into the buffer from an external interface. An input pointer indicates a next position for data to be read out to processing circuitry. An output pointer indicates a next position for data which has been processed by the processing circuitry to be returned to the buffer. A read pointer indicates a next position for data to be read out of the buffer to the external interface.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: November 14, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: Mark Leonard Buer
  • Patent number: 6145047
    Abstract: Level trigger mode interrupts are converted to edge trigger mode interrupts in a computer system. A circuit detects the occurrence of a level trigger mode interrupt request, and asserts an edge trigger mode interrupt request output. The edge trigger mode interrupt request remains asserted until an End of Interrupt input is asserted, indicating that the CPU has completed servicing the prior interrupt. The edge trigger mode interrupt request is then deasserted.
    Type: Grant
    Filed: May 19, 1994
    Date of Patent: November 7, 2000
    Assignee: VLSI Technology Inc.
    Inventors: Ned D. Garinger, Tein-Yow Yu
  • Patent number: 6143642
    Abstract: Disclosed is a method for making a programmable structure on a semiconductor substrate. The semiconductor structure has a first dielectric layer. The method includes plasma patterning a first metallization layer over the first dielectric layer. Forming a second dielectric layer over the first metallization layer and the first dielectric layer. Forming a plurality of tungsten plugs in the second dielectric layer. Each of the plurality of tungsten plugs are in electrical contact with the first metallization layer. Plasma patterning a second metallization layer over the second dielectric layer and the plurality of tungsten plugs, such that at least a gap over each of the tungsten plugs is not covered by the second metallization layer. Applying a programming electron dose to a portion of the second metallization layer.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: November 7, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Harlan Lee Sur, Jr., Subhas Bothra
  • Patent number: 6143613
    Abstract: A technique for processing an integrated circuit is disclosed. This technique includes the formation of a polysilicon resistor without silicide next to a polysilicon transistor gate with silicide. Prior to silicidation, an oxide layer coats both polysilicon structures. A portion of the oxide layer is removed by chemical-mechanical polishing to define a generally planar surface from the remaining oxide layer and reexposed portions of each polysilicon structure. A metal layer is deposited on the surface. The portion of the metal layer over the polysilicon resistor structure is removed through a lithographic procedure. A self-aligned silicidation procedure is performed to form a silicide from the metal remaining over the polysilicon gate structure. The formation of both structures is then completed.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: November 7, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: Xi-Wei Lin