Patents Assigned to VLSI Technology, Inc.
  • Patent number: 6141782
    Abstract: The present invention, generally speaking, provides an integrated circuit testing technique in which hardware accessibility of selected components is exploited in order to avoid scan insertion overhead but achieve as good or better fault coverage than if scan insertion had been used. The term "pseudo-scan" is used to refer to the use of read and write instructions to achieve the equivalent effect as scan insertion without the addition of scan flops. Existing ATPG tools may be used without modification by performing scan insertion on a "dummy" circuit and performing ATPG on the scan-augmented dummy circuit. The resulting ATPG vectors are then modified to perform pseudo scan of selected components of the original circuit.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: October 31, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Jerome Bombal, Laurent Souef
  • Patent number: 6134429
    Abstract: A system for a direct digital down conversion of a 10.8 MHz intermediate frequency signal in the personal handy phone system. The present invention includes a system that enables a direct digital down conversion of a 10.8 MHz intermediate frequency signal into a digital baseband signal within cell stations and portable stations of the personal handy phone system. To perform this direct digital down conversion of a 10.8 MHz intermediate frequency signal, one embodiment of the present invention uses a hard limiter circuit, a sampler circuit and a digital down converter circuit. The hard limiter circuit of the present invention receives a 10.8 MHz intermediate frequency signal, utilized within cell stations and portable station of the personal handy phone system, and provides a threshold for it. The sampler circuit uses a 19.2 MHz oscillating clock signal to sample the intermediate frequency signal that is output from the hard limiter circuit. Due to spectral leakage, the 10.
    Type: Grant
    Filed: April 10, 1998
    Date of Patent: October 17, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Patrick Feyfant, Laurent Winckel, Satoshi Yoshida, Philippe Gaglione, Varenka Martin, Oliver Weigelt, Denis Archambaud
  • Patent number: 6134662
    Abstract: A distributed firewall is utilized in conjunction with a memory-mapped serial communications interface such as that defined by the IEEE 1394 specification to permit secure data transmission between selected nodes over the interface. The distributed firewall incorporates security managers in the selected nodes that are respectively configured to control access to their associated nodes, thereby restricting access to such nodes to only authorized entities. The security manager in at least one of the nodes is implemented in the physical (PHY) layer for the communications interface. The security manager controls access to its associated node by selectively modifying data packets received from unauthorized entities in such a manner that acceptance of the modified data packets by the link layer is inhibited, e.g., by modifying the checksum in a data packet so that, upon receipt by the link layer of the associated node, the data packet is determined to be invalid by the link layer.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: October 17, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Paul S. Levy, Steve Cornelius
  • Patent number: 6130166
    Abstract: A CF.sub.4 /H.sub.2 O.sub.2 plasma is used to remove residues remaining after an ashing step. On a substrate, a layer of photoresist is formed over an underlying layer. The layer of photoresist is developed to form a photoresist pattern. The underlying layer is etched using the photoresist pattern. The substrate, including exposed areas of the underlying layer, are subjected to a plasma comprising H.sub.2 O.sub.2 vapor and a gaseous fluorocarbon to remove residual polymers.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: October 10, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: Edward Yeh
  • Patent number: 6127811
    Abstract: The present invention includes a micro-electromechanical system and voltage shifter, method of synchronizing an electronic system and a micromechanical system of a micro-electromechanical system. According to one aspect, the present invention provides a micro-electromechanical system voltage shifter including at least one node; a capacitor including plural opposing conductive plates; a micromechanical system configured to vary the capacitance of the capacitor; an electrical system configured to selectively couple the capacitor and the at least one node; and a mixer configured to output a product signal to synchronize the micromechanical system and the electrical system.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: October 3, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Jayarama N. Shenoy, Subhas Bothra
  • Patent number: 6118314
    Abstract: The present invention includes a circuit assembly and method of synchronizing plural circuits. According to one aspect of the present invention, a circuit includes: an oscillator configured to generate a reference clock signal; a first circuit including: a first divider configured to generate a first internal clock signal responsive to the reference clock signal; and reset generation circuitry configured to receive an external reset signal and generate a reset second circuit signal synchronized with a predefined position of the first divider, with the reference clock signal and with the external reset signal; and a second circuit including: reset detection circuitry configured to generate a reset detection signal synchronized with the reset second circuit signal and the reference clock signal; and a second divider configured to set to a predefined position responsive to the reception of the reset detection signal and generate a second internal clock signal synchronized with the first internal clock signal.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: September 12, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Patrick Arnould, Frederic Hayem
  • Patent number: 6118682
    Abstract: The present invention is directed to providing a storage device, such as a content addressable memory, which enables multiple matches to be simply and efficiently examined during a multiple match cycle, regardless of the size of the storage device. For example, where two matched entries in a content addressable memory correspond to a search address, exemplary embodiments reduce the task of examining the locations of these matches to processing only two matched addresses as opposed to having to match all entries of the content addressable memory. By providing an efficient access to multiple matched entries of a memory, the multiple matches can actually be used in an ordered manner to access different branches of a secondary memory. The use of a relatively simple control scheme enables the control logic to be implemented on a single integrated circuit chip with the memory device itself (e.g., a content addressable memory).
    Type: Grant
    Filed: July 7, 1998
    Date of Patent: September 12, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: William C. Martin
  • Patent number: 6114246
    Abstract: A method of using polish stop film to control dishing during copper chemical mechanical polishing. In one embodiment, the method comprises several steps. One step involves depositing a polish stop layer above a metal layer disposed on a semiconductor wafer. Another step involves placing the semiconductor wafer onto a polishing pad of a chemical mechanical polishing machine. A further step involves removing the metal layer of the semiconductor wafer and also preferentially removing the polish stop layer using a chemical mechanical polishing process. The benefit of the polish stop layer is to prevent dishing of the metal layer within the trench. Another step involves ceasing the chemical mechanical polishing process when the metal layer is removed from desired areas of the semiconductor wafer and the semiconductor wafer is substantially planar.
    Type: Grant
    Filed: January 7, 1999
    Date of Patent: September 5, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: Milind Weling
  • Patent number: 6115367
    Abstract: The present invention provides methods of analyzing a radio signal, including a personal handy-phone system radio signal. In accordance with a first aspect of the present invention, a method of analyzing a radio signal in a transceiver selectively coupled with a first antenna and a second antenna comprises: receiving a radio signal comprising a plurality of slots via the first antenna; first configuring the transceiver to receive via the first antenna; during the receiving of a selected slot, first determining a radio signal characteristic; following the first determining and during the receiving of the selected slot, second configuring the transceiver to receive via the second antenna; and following the second configuring and during the receiving of the selected slot, second determining a radio signal characteristic.
    Type: Grant
    Filed: August 5, 1997
    Date of Patent: September 5, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Denis Archambaud, Patrick Feyfant, Philippe Gaglione, Varenka Martin, Oliver Weigelt, Laurent Winckel, Satoshi Yoshida
  • Patent number: 6113647
    Abstract: A set of flat net descriptors are added to a hierarchical representation of a specified circuit design so as to provide a hierarchical view and a flat net view of the circuit design. The hierarchical representation includes a set of cell descriptors representing hierarchical cells in the specified circuit design, and a set of net descriptors representing portions of interconnections located within each hierarchical cell. Each net descriptor has associated therewith a list of endpoint descriptors representing endpoints of a corresponding one of the interconnections located within a respective hierarchical cell. The procedure for generating flat nets generates a flat net descriptor for each interconnection in the specified circuit. Each flat net descriptor has associated therewith a list of endpoint descriptors representing all endpoints of the interconnection.
    Type: Grant
    Filed: November 6, 1996
    Date of Patent: September 5, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Francois Silve, Arnold Ginetti
  • Patent number: 6108738
    Abstract: The present invention comprises a multiple bus master PCI (peripheral component interconnect) bus system within an integrated circuit. The system of the present includes an integrated circuit fabricated onto a single semiconductor die. An internal PCI bus is built into the integrated circuit. The internal PCI bus is adapted to transmit and convey data signals. A plurality of PCI agents are built into the integrated circuit. Each of the plurality of PCI agents are designed to perform a respective function and each of the plurality of PCI agents are coupled to the internal PCI bus to transmit and receive data. The internal PCI bus and the plurality of PCI agents are built into the integrated circuit on the single semiconductor die to create a high performance device.
    Type: Grant
    Filed: June 10, 1997
    Date of Patent: August 22, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Peter Chambers, David Gerard Spaniol, Ronald Lange
  • Patent number: 6107158
    Abstract: A shallow trench isolation structure and method for forming such structure. In one embodiment, the semiconductor device isolating structure of the present invention includes a trench formed into a semiconductor substrate. A cross-section of the trench has a first sidewall sloping inwardly towards the center of a substantially planar bottom surface, and a second sidewall sloping inwardly towards the center of the substantially planar bottom surface. Additionally, a cross section of the trench has a first rounded bottom trench corner at an interface of the first sidewall and the substantially planar bottom surface, and a second rounded bottom trench corner at an interface of the second sidewall and the substantially planar bottom surface.
    Type: Grant
    Filed: March 25, 1998
    Date of Patent: August 22, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Jie Zheng, Calvin Todd Gabriel, Suzanne Monsees
  • Patent number: 6104254
    Abstract: The present invention comprises a CMOS voltage controlled oscillator (VCO) circuit for operation at frequencies of 1 GHz and above. The circuit of the present invention includes a voltage-to-current converter circuit for receiving a VCO input, a replica circuit coupled to the voltage-to-current converter circuit, and a first and second VCO cell coupled to the replica circuit. The first and second VCO cells are also coupled to one another. The circuit of the present invention also includes a VCO output for transmitting a VCO output signal. A first current source is coupled to the first VCO cell to transmit a first current from a power supply to the first VCO cell. A second current source is coupled to the second VCO cell to transmit a second current from the power supply to the second VCO cell.
    Type: Grant
    Filed: November 18, 1997
    Date of Patent: August 15, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: Kamran Iravani
  • Patent number: 6104589
    Abstract: The present invention includes integrated circuitry, an interface circuit of an integrated circuit device, cascode circuitry, method of protecting an integrated circuit, method of operating integrated circuitry, and method of operating cascode circuitry. One aspect of the present invention provides integrated circuitry including a driver adapted to couple with a pad and internal circuitry of an integrated circuit device, the driver includes a first transistor coupled with the pad; cascode circuitry including a second transistor coupled with the pad and a third transistor coupled with ground, the cascode circuitry configured to remain in an untriggered state during the presence of stress currents at the pad; and protection circuitry intermediate the pad and ground and configured to shunt stress currents from the pad to ground.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: August 15, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: Jon R. Williamson
  • Patent number: 6105142
    Abstract: A method and apparatus for managing power consumption in a computer system wherein the method and apparatus is compliant with the proposed Advanced Configuration and Power Interface (ACPI) specification. In one embodiment, a power management processor is sandwiched between platform hardware and the ACPI register layer. The processor processes all operating power management commands and requests while remaining transparent to the user and the operating system. In so doing, routine power management functions, so classified by the operating system, are implemented by the operating system. Sophisticated power management features, on the other hand, are implemented by the present invention independent from operating system control. Accordingly, in the present invention, the operating system need not suspend processing of other threads to process sophisticated power management procedures.
    Type: Grant
    Filed: February 11, 1997
    Date of Patent: August 15, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Lonnie C. Goff, David R. Evoy, Franklyn Story, Mark Sullivan
  • Patent number: 6103634
    Abstract: A method for fabricating semiconductor devices that allows for the integration of anti-reflective coatings into the fabrication process. A method for removing an inorganic anti-reflective coating is disclosed that includes the step of exposing the layer of inorganic anti-reflective coating to atomic fluorine. An asher is used to generate fluorine atoms from NF.sub.3 precursor gas. The NF.sub.3 precursor gas is mixed with an inert carrier such as helium. In one embodiment, sequential etch steps are performed in an asher so as to sequentially remove both a layer of photoresist and a layer of inorganic anti-reflective coating.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: August 15, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: Samuel Vance Dunton
  • Patent number: 6104220
    Abstract: A single-ended power supply under-voltage level detection circuit included first and second stages of devices stacks coupled between a power supply signal and a reference potential. As the power supply increases it overcomes device threshold voltages in the first stage causing it to enable the second stage. As the power supply signal continues to increase and reaches a second voltage level, the second stage outputs a level indicator signal which indicates that the power supply is greater than or equal to a predetermined voltage level. A power-down signal can be externally applied to devices in the first and second stages so as to disable the detection circuit no matter what the power supply signal level is. In addition, the detection circuit can be used in a power-on-reset (POR) circuit to detect when the power supply has reached a predetermined voltage level so as to cause the POR circuit to output a POR signal an extended time interval afterwards.
    Type: Grant
    Filed: January 20, 1998
    Date of Patent: August 15, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: John C. Ciccone
  • Patent number: 6101605
    Abstract: To perform a secure operation, an original encrypted value is obtained from a memory. The original encrypted value is decrypted to obtain an original value and an original validity code. The original validity code is compared with a stored validity code. If the original validity code is equivalent to the stored validity code, the secure operation is performed on the original value to produce a new value. Then a permanent alteration is made to the stored validity code to produce a new stored validity code. The new value and the new stored validity code are encrypted to produce a new encrypted value. The new encrypted value is stored in the memory.
    Type: Grant
    Filed: May 15, 1997
    Date of Patent: August 8, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: Mark Leonard Buer
  • Patent number: 6094965
    Abstract: Semiconductor wafer coating system calibration structures and methods are described. In one embodiment, a calibration structure includes a perimetral edge bounding a calibration body. A calibration edge is spaced from the perimetral edge and is positioned over the calibration body. Together, the edges define a distance therebetween which is configured to calibrate a wafer coating system. In a preferred embodiment, the edges define respective termination distances configured to calibrate multiple different wafer coating systems. In another embodiment, a calibration pattern is formed over a semiconductor wafer. A layer of material is formed over the calibration pattern by a coating system, and selected portions thereof removed by the system. The positions of unremoved portions of the layer of material are inspected relative to the calibration pattern to ascertain whether the coating system removed the selected portions within desired tolerances.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: August 1, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Walter B. Hubbard, Lisa Napolitano
  • Patent number: RE36893
    Abstract: An anti-fuse structure formed in accordance with the present invention includes a conductive layer base. A layer of anti-fuse material overlies the conductive base layer. On top of the anti-fuse layer is an insulating layer, in which a via hole is formed to the anti-fuse layer. The lateral dimension of the via hole is less than about 0.8 microns. Provided in the via hole is a conductive non-Al plug including a conductive barrier material such as TiN or TiW to contact the anti-fuse material and overlie the insulating layer. Tungsten is effectively used as the non-Al plug. An electrically conductive layer is formed over the plug and is separaged from the anti-fuse layer by at least one-half the depth of the via hole. The structure is then programmable by application of a programming voltage and readable by application of a sensing voltage, which is lower than the programming voltage.
    Type: Grant
    Filed: February 6, 1997
    Date of Patent: October 3, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Dipankar Pramanik, Subhash R. Nariani