Abstract: A system for transforming computer system interrupts from state based interrupts to event based interrupts. The system of the present invention includes an interrupt acknowledge detection circuit adapted to detect an interrupt acknowledge from a computer system. The interrupt acknowledge detect circuit is coupled to a vector match circuit. The vector match circuit is adapted to receive an interrupt vector from the computer system and determine whether the interrupt vector matches a predetermined interrupt vector within the vector match circuit. The vector match circuit is, in turn, coupled to an interrupt assertion circuit. The interrupt assertion circuit includes an internal interrupt request line and an external interrupt request line. The interrupt assertion circuit functions by asserting an interrupt signal via the external interrupt request line to the computer system in response to receiving a state based interrupt via the internal interrupt request line.

Abstract: An optimal gap is determined between a lower electrode and an upper electrode in a plasma processing device. A gap is set between the lower electrode and the upper electrode, and a substrate is processed in the plasma processing chamber. The processing results are obtained, and the processing rate and uniformity are determined from the processing results. The processing rate and uniformity are plotted with the gap setting. The steps of setting, processing, obtaining, determining, and plotting are repeated for additional substrates, the gap setting being different for each substrate. The optimal gap setting is selected as the gap setting corresponding to an optimal processing rate and an optimal uniformity.

Abstract: A method of forming a focus/exposure matrix on a wafer is provided, wherein the wafer is used to calibrate the photostepper's focus and exposure time settings. The focus/exposure matrix comprising a series of patterns disposed on the wafer. The patterns being arranged in rows and columns. The patterns in a row being characterized by having been formed with substantially the same exposure time and an effective focus that increments between successive row patterns by an amount substantially corresponding to half the focus resolution of the photostepper. The patterns in a column being characterized by having been formed with substantially the same effective focus and an exposure time that increments between successive column patterns by a finite amount.

Abstract: There is provided herein a joystick interface which includes circuitry to detect when the joystick output signal has been at a steady-state level for a predetermined period of time and upon detection of that condition, the circuitry powers down at least some of the circuitry associated with providing the digital signal representation to the computer. In one particular embodiment of the invention, analog circuitry including a slope detector, makes use of two non-overlapping clocks to sample data and provide it to a comparator. The comparator is used to determine if there has been any change between consecutive or sequential samples, representative of joystick shaft movement. After a predetermined number of comparisons showing no change in either a neutral joystick position or a non-neutral joystick position, the digital circuitry is powered-down to a reduced power operating mode.

Abstract: A method and apparatus for locating the user of a computer system and adjusting the sound from the system speakers. The computer system includes a computer, two speakers, a microphone, a signal processor, and an audio processor. The speakers emit a sound which is reflected from the user and other objects in the vicinity of the system. The invention includes an algorithm for determining which of the reflected sounds had been reflected from the user of the computer system. The character of the sound emitted by the computer system is then adjusted to enhance the sound effects at the location of the user.

Abstract: A system for optimizing arbitration latency of a bus. The system places a bus grant idle state insertion logic block in parallel with a bus grant decision logic block. This allows the bus grant idle state insertion logic block to immediately deassert all bus grant output signals for one clock cycle as long as the bus is idle and a device has requested use of the bus. The bus grant idle state insertion logic block then changes the output of a multiplexer so as to select the bus grant output signal (which becomes valid during this state)and drives the output bus grant signal off chip thereby granting the bus to a device which requested use of the bus. The bus granting process takes two (2) clock cycles.

Abstract: A multiple peripheral component interconnect (PCI) agent integrated circuit device for connecting to an external PCI bus. In one embodiment, the present multiple PCI agent integrated circuit device includes, an integrated circuit which is adapted to be coupled to an external PCI bus. The integrated circuit includes an internal PCI bus built in. The internal PCI bus is adapted to transmit data signals thereon, and is further adapted to couple to the external PCI bus via a connector. A plurality of PCI agents are built into the integrated circuit, wherein each of the plurality of PCI agents are capable of performing an independent function. Each of the plurality of PCI agents are coupled to the internal PCI bus. A predictive arbiter is built into the integrated circuit and is coupled to both the internal PCI bus and to the plurality of PCI agents. The predictive arbiter arbitrates between the PCI agents for ownership of the internal PCI bus.

Abstract: A method for fabricating a chip size package is provided. The method includes the step of forming a laminated substrate which consists of a dielectric layer and a highly conductive layer disposed thereon. Holes are drilled into the dielectric layer. A desired pattern is applied to the conductive layer. A chip structure is formed which consists of a silicon die and an insulating layer disposed thereon. Gold bumps are applied to the top surface of the bonding pads. The laminated substrate is bonded to the chip structure via the holes and gold bumps. A solder mask is applied over the top surface of the conductive layer of the laminated substrate so as to form selective solder areas. Finally, solder balls are attached to the selective solder areas.

Abstract: A mixed voltage compatible buffer having reduced power consumption is provided. One embodiment of the buffer according to the present invention comprises: a data input configured to receive an output data signal; a data interface configured to couple with a pad interconnect; an output driver coupled with said data interface and being configured to apply the output data signal thereto; and a data controller intermediate said data input and said output driver, said data controller being configured to apply a plurality of control signals of substantially equal voltage to said output driver to control the operation thereof responsive to the output data signal received via said data input. The present invention also provides for a method of transferring data within the buffer.

Abstract: A method of improving the planarity of spin-on-glass layers in semiconductor wafer processing is disclosed. Gaps in between active conductive traces in a trace layer that exceed a predetermined distance are provided with dummy lines having a specific geometry in order to improve the planarity achieved in subsequently applied spin-on glass layers. In some embodiments, the predetermined distance is greater than approximately 1 micrometer, as for example in the range of approximately 3 to 6 micrometers. In some applications, both the active conductive traces and the dummy lines are formed from a metallic material that is deposited in one single step with a passivation layer being deposited over both the conductive traces and the raised lines prior to application of the spin-on glass layer.

Abstract: A data processing system includes a microprocessor, memory, and an instruction substitution filter. The microprocessor has separate data and instruction caches. The filter includes configuration memory that occupies memory mapped I/O space. Configuration data indicating instruction types to be deimplemented is entered into the filter during a boot sequence. Once configured, the filter substitutes call instructions for the deimplemented instructions. When executed, the call instructions activate a substitution routine that determines the address of the deimplemented instruction and then performs a data read of the unfiltered deimplemented instructions and then implements the function that the deimplemented function was intended to implement (but, due to microprocessor defects, does not). Accordingly, the present invention allows a microprocessor with defectively implemented instructions to be used as intended with minimal performance penalties.

Abstract: A packet-data FIFO buffer system comprises a FIFO buffer with a series of FIFO memory locations. Each FIFO memory location includes a data section for storing a packet data word and a flag section for storing an indication of whether or not the associated data section includes the last word of a packet. The FIFO buffer capacity is not limited to the number of maximum length packets it can hold; instead, a greater number of small packets can be stored. This increases the effectiveness of available FIFO memory and minimizes communication delays along the channels serviced by the FIFO. The FIFO design is simple and fairly self contained so that minimal external logic and control is required. In addition, an indication of the presence or absence of a complete data packet in the FIFO buffer can be easily obtained by logically adding (ORing) the contents of the flag sections.

Abstract: The present invention is directed to a method and apparatus for synchronizing one or more data signal lines of a data bus to multiple clocks, and for guaranteeing the validity of the synchronized values. Exemplary embodiments avoid the need to eliminate delays between the asynchronous clocks. Thus, exemplary embodiments of the present invention can be used for reliably synchronizing the in-pointer and out-pointer of a first-in first-out memory.

Abstract: An antifuse structure is formed between two metal contacts in which a thin oxide layer is formed on the first or bottom metal, a shallow via is provided oxide layer and a layer of amorphous silicon is deposited over the thin oxide and into the shallow via without leaving the usual furrows in the amorphous silicon and thereby eliminating the step coverage problems of cusps forming in the subsequently applied second or top metal.

Abstract: A focus/exposure matrix comprises a series of patterns disposed on a wafer. The patterns are arranged in rows and columns. The patterns in a row are characterized by having been formed with substantially the same exposure time and an effective focus that increments between successive row patterns by an amount substantially corresponding to half the focus resolution of the photostepper. The patterns in a column are characterized by having been formed with substantially the same effective focus and an exposure time that increments between successive column patterns by a finite amount.

Abstract: An automated routing tool for routing interconnections between circuit elements, standard cells and/or cell blocks of cell-based designs which incorporates the best features of both currently known gate array routing techniques with currently known cell-based routing techniques. The invention eliminates the disadvantages of permitting the detailed router to adjust the relative positions of the circuit elements, standard cells and/or cell blocks during the detailed routing process. The method employs a topology manager which iteratively compacts the circuit topology while at the same time optimizing the routing of the interconnections among the circuit elements, standard cells and/or cell blocks of the circuit design. The method employs bin-based global routing, which identifies expandable boundaries and which provides input to a compaction routine which expands or contracts the expandable areas in accordance with the result of the global routing process.

Abstract: A keyboard controller for a computer system with integrated Real Time Clock (RTC) functionality. The keyboard controller has a microprocessor for controlling peripheral device bus traffic such as keyboard and mouse traffic. The microprocessor also acts as a boot device for the computer system. By programming the microprocessor to emulate RTC functions, adding a divider circuit, and having an I/O support block which stores RTC registers and an extended CMOS RAM memory block, the entire RTC FSB along with its power detection and switching circuit can be removed.

Abstract: A method of improving the planarity of spin-on glass layers in semiconductor wafer processing is disclosed. Gaps in between active conductive traces on a trace layer of a semiconductor wafer that exceed a predetermined threshold distance are provided with dummy surfaces arranged in a micro-pattern in order to improve the planarity achieved in subsequently applied spin-on glass layers. In some embodiments, the predetermined threshold distance is greater than approximately 2 micrometers, as for example in the range of approximately 4.65 to 5 micrometers. In some applications, both the active conductive traces and the dummy surfaces are formed from a metallic material that is deposited in one single step with a dielectric layer being deposited over both the active conductive traces and the dummy surfaces prior to application of the spin-on glass layer.

Abstract: A high density leaded ball-grid array package for packaging an integrated-circuit die includes a laminated substrate formed of a non-conductive layer sandwiched between first and second conductive trace patterns. A leadframe is directly attached onto the first conductive trace pattern of the laminated substrate by a non-conductive adhesive so that the open portion thereof overlies a central region of the laminated substrate. An integrated-circuit die is mounted in the central region of the laminated substrate. Bonding wires are interconnected between bonding pads formed on the integrated-circuit die and bonding fingers formed on the leadframe. A plastic material is molded over the top surface of the die, bonding fingers and bonding wires. A solder mask is applied on the second conductive trace pattern so as to form selective solderable areas. Finally, solder balls are attached to the selective solderable areas.

Abstract: The present invention relates to a process control monitoring system and method. The system and method uses current comparator circuits for monitoring process changes. Process sensitive current sources are compared with weighted reference current sources in a manner that each output of the current comparators demonstrates the inequality of the current sources. By setting the weighted reference current sources properly, the outputs of the current comparators may be used to locate the process corner of the fabricated integrated circuit.