Abstract: A power semiconductor device includes semiconductor layer structure comprising a semiconductor drift region of a first conductivity type and an edge termination region comprising a plurality of guard rings of a second conductivity type. The guard rings extend into a surface of the semiconductor drift region. The guard rings respectively comprise a first portion adjacent the surface and a second portion spaced from the surface, where the first portion is wider than the second portion. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor device includes a semiconductor layer structure and a gate formed in a gate trench in the semiconductor layer structure. The gate trench has a bottom surface comprising a first portion at a first level and a second portion at a second level, different from the first level. A method of forming a semiconductor device includes providing a semiconductor layer structure, etching a first gate trench into the semiconductor layer structure, etching a second gate trench into the semiconductor layer structure, and performing an ion implantation into a bottom surface of the second gate trench. The second gate trench is deeper than the first gate trench, and at least a portion of the second gate trench is connected to the first gate trench.

Abstract: An electronics arrangement comprises an electrically insulative substrate comprising a top side and a bottom side. The electronics arrangement further comprises an inductor, a capacitor, or both. The electronics arrangement further comprises a thermally conductive heat transfer structure operative to transfer heat away from the ferrite core, the capacitor, or both.

Abstract: A semiconductor device comprises a semiconductor layer structure that has a gate trench therein and a source metallization layer on the semiconductor layer structure. The semiconductor layer structure comprises a drift region having a first conductivity type, a trench shield that has a second conductivity type, the trench shield positioned underneath the gate trench, and a trench shield connection pattern that has the second conductivity type, the trench shield connection pattern electrically connecting the trench shield to the source metallization layer, where the trench shield connection pattern extends deeper into the semiconductor layer structure than the trench shield.

Abstract: A transistor device includes a substrate and a plurality of transistor unit cells arranged in parallel on the substrate. Each of the transistor unit cells includes a source contact, a drain contact, and a gate finger between the source contact and the drain contact. The gate finger extends in a first direction and has a first end and a second end. The transistor device further includes a first solder bump on the transistor device that is within a periphery of the active region of the device and is electrically connected to the gate finger of a first one of the unit cells at a feed point that is between the first end and the second end of the gate finger.

Abstract: Transistors are provided that comprise a silicon carbide based semiconductor layer structure, a first current terminal, a second current terminal, a gate terminal, and a minimum gate terminal-to-second current terminal voltage clamp circuit in the semiconductor layer structure that is coupled between the gate terminal and the second current terminal.

Abstract: A semiconductor device comprises a silicon carbide based semiconductor layer structure and a first gate trench extending into an upper portion of the semiconductor layer structure. The semiconductor layer structure comprises a drift region having a first conductivity type, a well layer having a second conductivity type, and a support shield having the second conductivity type. A width of a first segment of the support shield that is deeper in the semiconductor layer structure than the well layer and less deep in the semiconductor layer structure than a bottom of the first gate trench decreases with increasing distance from the well region.

Abstract: A semiconductor device includes an active region comprising a plurality of alternating trenches and mesas in an epitaxial layer, the plurality of alternating trenches and mesas extending in a first direction, and an edge termination region adjacent the active region and including a first edge termination region and a second edge termination region. The edge termination region includes first and second guard ring trenches adjacent the active region that are separated by a termination mesa that extends in the first direction in the first edge termination region and extends in a second direction, perpendicular to the first direction, in the second edge termination region. The termination mesa has a first width in the first edge termination region and the termination mesa has a second width in the second edge termination region that is different from the first width.

Abstract: A semiconductor device comprises a silicon carbide based semiconductor layer structure that includes a drift layer having a first conductivity type, a gate trench that extends to a first depth into an upper surface of the semiconductor layer structure, a gate electrode in the gate trench, a support shield trench that extends to a second depth into the upper surface of the semiconductor layer structure, where the second depth is less than the first depth, and a source metallization layer on the upper surface of the semiconductor layer structure and extending into the support shield trench.

Abstract: A semiconductor die includes a drift region, an active region in the drift region, and an edge termination region surrounding the active region in the drift region. The drift region has a first doping type. The edge termination region includes a charge compensation region, a number of guard rings, and a counter doping region. The charge compensation region is in the drift region and has a second doping type that is opposite the first doping type. The guard rings are in the charge compensation region, have the second doping type, and a doping concentration that is greater than a doping concentration of the charge compensation region. The counter doping region is in the drift region and overlaps at least a portion of the charge compensation region. The counter doping region has the first doping type.

Abstract: A semiconductor package includes a metal submount; at least one transistor die arranged on said metal submount; and one or more metal contacts configured to be located adjacent said metal submount by a connection. The connection is configured as one of the following: a spot welded portion, a laser beam modified portion, a laser beam welded portion, an ultrasonic welded portion, an electric resistance welded portion, and a fused metal welded portion.

Abstract: A process includes measuring at least one component parameter of a plurality of components with a testing device; and arranging at least a portion of the plurality of components in a sequential order based on the at least one component parameter with an implementation system in at least one of the following: a shipping format and a device implementation of the portion of the plurality of components. A system is disclosed as well.

Abstract: A device includes at least one semiconductor device; a package support configured to support the at least one semiconductor device; electrical connection portions having at least one of the following: electrical connection portions extending from the package support, electrical connection portions configured as a bond wire device connection, electrical connection portions configured as a bump ball connection, and/or electrical connection portions configured as a stud bump connection. Where the electrical connection portions connect between the at least one semiconductor device and the package support.

Abstract: A semiconductor die includes a semiconductor body, and a multi-layer environmental barrier on the semiconductor body. The multi-layer environmental barrier includes a plurality of sublayers that are stacked on the semiconductor body. Each of the sublayers comprises a respective stress in one or more directions, where the respective stresses of at least two of the sublayers are different. The sublayers may include a first stressor sublayer comprising first stress, and a second stressor sublayer comprising a second stress that at least partially compensates for the first stress in the one or more directions. Related devices and methods of fabrication are also discussed.

Abstract: Transistor devices are provided. In one example, the transistor device includes a channel layer. The transistor device includes a multilayer barrier structure on the channel layer. The multilayer barrier structure includes a first Group III-nitride layer and a second Group III-nitride layer on the first Group III-nitride layer and opposite to the channel layer. The first Group III-nitride layer has a thickness greater than a thickness of the second Group III-nitride layer. An aluminum concentration of the first Group III-nitride layer is at least two times greater than an aluminum concentration of the second Group III-nitride layer.

Abstract: A power semiconductor device includes a semiconductor layer structure comprising a wide bandgap semiconductor material. The semiconductor layer structure includes a drift region of a first conductivity type, a source region of the first conductivity type, and a well contact region of a second conductivity type adjacent the source region. A first ohmic contact comprising a first conductive material is formed on the source region. A second ohmic contact comprising a second conductive material, which is different than the first conductive material, is formed on the well contact region. A gate structure is formed on the drift region and includes a gate contact comprising a third conductive material, which is different than the first and second conductive material. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor die includes a semiconductor body having a gate, a source contact, and a drain contact thereon, a metal contact structure on the semiconductor body and electrically connected to the gate, the source contact, or the drain contact, and an encapsulation structure. The encapsulation structure includes first and second encapsulation layers of respective non-conductive materials stacked on the metal contact structure, and an opening extending therethrough to expose the metal contact structure. The opening includes a sidewall having a substantially continuous slope that extends through the first and second encapsulation layers to the metal contact structure. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor device includes a semiconductor layer structure having a drift region of a first conductivity type and a well region of a second conductivity type above the drift region. A gate is provided on the semiconductor layer structure adjacent the well region. A buried shielding structure of the second conductivity type is provided under the well region and separated from the well region by a portion of the drift region. Related devices and fabrication methods are also discussed.