Abstract: Transistor devices are provided. In one example, the transistor device includes a channel layer. The transistor device includes a multilayer barrier structure on the channel layer. The multilayer barrier structure includes a first Group III-nitride layer and a second Group III-nitride layer on the first Group III-nitride layer and opposite to the channel layer. The first Group III-nitride layer has a thickness greater than a thickness of the second Group III-nitride layer. An aluminum concentration of the first Group III-nitride layer is at least two times greater than an aluminum concentration of the second Group III-nitride layer.

Abstract: A power semiconductor device includes a semiconductor layer structure comprising a wide bandgap semiconductor material. The semiconductor layer structure includes a drift region of a first conductivity type, a source region of the first conductivity type, and a well contact region of a second conductivity type adjacent the source region. A first ohmic contact comprising a first conductive material is formed on the source region. A second ohmic contact comprising a second conductive material, which is different than the first conductive material, is formed on the well contact region. A gate structure is formed on the drift region and includes a gate contact comprising a third conductive material, which is different than the first and second conductive material. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor die includes a semiconductor body having a gate, a source contact, and a drain contact thereon, a metal contact structure on the semiconductor body and electrically connected to the gate, the source contact, or the drain contact, and an encapsulation structure. The encapsulation structure includes first and second encapsulation layers of respective non-conductive materials stacked on the metal contact structure, and an opening extending therethrough to expose the metal contact structure. The opening includes a sidewall having a substantially continuous slope that extends through the first and second encapsulation layers to the metal contact structure. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor device includes a semiconductor layer structure having a drift region of a first conductivity type and a well region of a second conductivity type above the drift region. A gate is provided on the semiconductor layer structure adjacent the well region. A buried shielding structure of the second conductivity type is provided under the well region and separated from the well region by a portion of the drift region. Related devices and fabrication methods are also discussed.

Abstract: Power semiconductor devices comprise a silicon carbide based semiconductor layer structure including an active region defined therein and a gate bond pad that is on the semiconductor layer structure and vertically overlaps the active region.

Abstract: A transistor device package includes a component assembly comprising an interconnect structure, a transistor die having a front surface including gate, drain, and source terminal on a first surface of the interconnect structure, and one or more passive electrical components electrically coupled to the gate, drain, and/or source terminal by the interconnect structure. A thermally conductive flange is attached to a back surface of the transistor die, which is opposite the front surface, by a conductive adhesive. Respective patterns of the conductive adhesive are provided on the first surface of the interconnect structure, and least one of the respective patterns of the conductive adhesive provides an input, output, or ground signal path for the transistor device package. Related fabrication methods are also discussed.

Abstract: A wide band-gap semiconductor layer structure is provided that comprises a drift region having a first conductivity type and a plurality of source regions having the first conductivity type on the drift region. A plurality of trenches are provided in an upper surface of the wide band-gap semiconductor layer structure. Second conductivity type dopants are implanted into the wide band-gap semiconductor layer structure to simultaneously form well regions underneath the source regions and trench shielding regions underneath the trenches, the well regions and the trench shielding regions each having a second conductivity type.

Abstract: A vertical field effect device having a body, gate dielectric, and a gate electrode, which is in a trench that extends into the body from the top surface of the body and is located between first and second source regions. The first and second regions vertically overlap the gate electrode. The first and second channel regions laterally overlap a bottom of the gate electrode, such that each channel formed in the first and second source regions have a horizontal segment where the first and second channel regions laterally overlap the bottom of the gate electrode. In another embodiment, the first and second channel regions also vertically overlap the gate electrode such that each channel formed in the first and second source regions also have a vertical segment where the first and second channel regions vertically overlap the gate electrode.

Abstract: A semiconductor device includes a semiconductor layer structure comprising a gate trench formed in an upper surface thereof, a gate finger in the gate trench, a supplemental dielectric layer on an upper surface of the gate finger and vertically overlaps the gate trench, and a gate connector on an upper surface of the supplemental dielectric layer and on an upper surface of the gate finger.

Abstract: In some aspects, a device includes a substrate. A first metallization arranged on the substrate. A second metallization arranged on the substrate. A circuit arranged on the substrate and electrically connected to the first metallization and the second metallization. The first metallization and the second metallization being configured, structured, and arranged to make a solder connection to a device, where the substrate may include silicon carbide (SiC).

Abstract: Systems and methods for grinding semiconductor workpieces are provided. In one example, a method includes providing a surface of the semiconductor workpiece against a grinding apparatus. The grinding apparatus includes an abrasive surface. The method further includes imparting relative motion between the abrasive surface and the semiconductor workpiece to implement a grinding operation on the semiconductor workpiece. The method further includes providing a fluid to the surface of the semiconductor workpiece or the abrasive surface during the grinding operation. The fluid includes an additive. The additive includes one or more of an oxidizing agent, an etchant, a surfactant, or a lubricant.

Abstract: A semiconductor die includes a semiconductor body, and a multi-layer environmental barrier on the semiconductor body. The multi-layer environmental barrier includes first and second sublayers of first and second oxide materials, respectively, where the first oxide material is different than the second oxide material. Related devices and fabrication methods are also discussed.

Abstract: A crystalline material processing method includes forming subsurface laser damage at a first average depth position to form cracks in the substrate interior propagating outward from at least one subsurface laser damage pattern, followed by imaging the substrate top surface, analyzing the image to identify a condition indicative of presence of uncracked regions within the substrate, and taking one or more actions responsive to the analyzing. One potential action includes changing an instruction set for producing subsequent laser damage formation (at second or subsequent average depth positions), without necessarily forming additional damage at the first depth position. Another potential action includes forming additional subsurface laser damage at the first depth position.

Abstract: A transistor device includes a metal submount; a transistor die arranged on said metal submount; an IPD component arranged on said metal submount, and the IPD component having a baseband damping resistor arranged on a thermally conductive dielectric substrate; and a second IPD component arranged on said metal submount, and the second IPD component may include a baseband decoupling capacitor arranged on a thermally conductive dielectric substrate.

Abstract: Die attach materials are provided. In one example, the die-attach material includes a plurality of core-shell particles. Each core-shell particle includes a core and a shell on the core. The core includes a conducting material. The shell includes a metal nitride.

Abstract: A transistor device ac includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher bandgap than the channel layer, a source contact and a drain contact on the barrier layer, and a gate contact on the barrier layer between source contact and the drain contact. The device further includes a plurality of selective modified access regions at an upper surface of the barrier layer opposite the channel layer. The selective modified access regions include a material having a lower surface barrier height than the barrier layer, and the plurality of selective modified access regions are spaced apart on the barrier layer along a length of the gate contact.

Abstract: Field reducing structures for transistor devices having Group III-nitride semiconductor structures are provided. In one example, a transistor device includes a nitrogen-polar (N-polar) Group III-nitride semiconductor structure. The transistor device includes a source contact, a drain contact, and a gate contact. The transistor device includes a field reducing structure operable to reduce an electric field in a region in the N-polar Group III-nitride semiconductor structure between the gate contact and the drain contact.

Abstract: An apparatus configured to reduce lag includes a substrate; a group III-Nitride back barrier layer on the substrate; a group III-Nitride channel layer on the group III-Nitride back barrier layer; a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer include a higher bandgap than a bandgap of the group III-Nitride channel layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a p-region being arranged at or below the group III-Nitride barrier layer. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain.