Abstract: A transistor device includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, a source contact and a drain contact on the barrier layer, an insulating layer on the semiconductor layer between the source contact and the drain contact, and a gate contact on the insulating layer. The gate contact includes a central portion that extends through the insulating layer and contacts the barrier layer and a drain side wing that extends laterally from the central portion of the gate toward the drain contact by a distance ?D. The drain side wing of the gate contact is spaced apart from the barrier layer by a distance d1 that is equal to a thickness of the insulating layer. The distance ?D is less than about 0.3 ?m, and the distance d1 is less than about 80 nm.

Abstract: Gallium nitride based RF transistor amplifiers include a semiconductor structure having a gallium nitride based channel layer and a gallium nitride based barrier layer thereon, and are configured to operate at a specific direct current drain-to-source bias voltage. These amplifiers are configured to have a normalized drain-to-gate capacitance at the direct current drain-to-source bias voltage, and to have a second normalized drain-to-gate capacitance at two-thirds the direct current drain-to-source bias voltage, where the second normalized drain-to-gate capacitance is less than twice the first normalized drain-to-gate capacitance.

Abstract: A transistor device includes a transistor cell comprising a channel region, a gate runner that is electrically connected to a gate electrode on the channel region and physically separated from the gate electrode, and a harmonic termination circuit electrically connected to the gate runner between the gate electrode and an input terminal of the transistor device, the harmonic termination circuit configured to terminate signals at a harmonic frequency of a fundamental operating frequency of the transistor device.

Abstract: An integrated circuit device includes a radio frequency transistor amplifier die having a first surface, a second surface, a semiconductor layer structure that is between the first and second surfaces and includes a plurality of transistor cells adjacent the first surface, and terminals coupled to the transistor cells. At least one passive electronic component is provided on the second surface of the die and is electrically connected to at least one of the terminals, for example, by at least one conductive via. One or more conductive pillar structures may protrude from the first surface of the die to provide electrical connections to one or more of the terminals.

Abstract: Semiconductor devices and methods of forming the devices are provided. Semiconductor devices include a semiconductor layer structure comprising a trench in an upper surface thereof, a dielectric layer in a lower portion of the trench, and a gate electrode in the trench and on the dielectric layer opposite the semiconductor layer structure. The trench may include rounded upper corner and a rounded lower corner. A center portion of a top surface of the dielectric layer may be curved, and the dielectric layer may be on opposed sidewalls of the trench. The dielectric layer may include a bottom dielectric layer on a bottom surface of the trench and on lower portions of the sidewalls of the trench and a gate dielectric layer on upper portions of the sidewalls of the trench and on the bottom dielectric layer.

Abstract: A circuit includes a field effect transistor (FET), a reference transistor having an output coupled to an output of the FET, an active bias circuit coupled to the reference transistor and configured to generate an input signal for the reference transistor in response to a change in drain current of the reference transistor due to carrier trapping and to apply the input signal to an input of the reference transistor, and a summing node coupled to an input of the FET and to the input of the reference transistor. The summing node adds the input signal to an input signal of the FET to compensate the carrier trapping effect.

Abstract: A transistor amplifier package includes a base, one or more transistor dies on the base, first and second leads coupled to the one or more transistor dies and defining respective radio frequency (RF) signal paths, and an isolation structure on the base between the respective RF signal paths. The isolation structure includes first and second wire bonds. The first and second wire bonds may have a crossed configuration defining at least one cross point therebetween. Related wire bond-based isolation structures are also discussed.

Abstract: A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at P1DB during operation of the power amplifier between 26.5 GHz and 30.5 GHz.

Abstract: A power semiconductor device comprises a semiconductor layer structure having a wide band-gap drift region having a first conductivity type, a gate trench having first and second opposed sidewalls that extend in a first direction in an upper portion of the semiconductor layer structure, first and second well regions having a second conductivity type in the upper portion of the semiconductor layer structure, the first well region comprising part of the first sidewall and the second well region comprising part of the second sidewall. A deep shielding region having the second conductivity type is provided underneath the gate trench, and a plurality of deep shielding connection patterns that have the second conductivity type are provided that electrically connect the deep shielding region to the first and second well regions. The deep shielding connection patterns are spaced apart from each other along the first direction.

Abstract: Semiconductor devices, and more particularly semiconductor devices with improved edge termination structures are disclosed. A semiconductor device includes a drift region that forms part of an active region. An edge termination region is arranged along a perimeter of the active region and also includes a portion of the drift region. The edge termination region includes one or more sub-regions of an opposite doping type than the drift region and one or more electrodes may be capacitively coupled to the drift region by way of the one or more sub-regions. During a forward blocking mode for the semiconductor device, the one or more electrodes may provide a path that draws ions away from passivation layers that are on the edge termination region and away from the active region. In this manner, the semiconductor device may exhibit reduced leakage, particularly at higher operating voltages and higher associated operating temperatures.

Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.

Abstract: A packaged radio frequency transistor amplifier includes a package housing, an RF transistor amplifier die that is mounted within the package housing, a first capacitor die that is mounted within the package housing, an input leadframe that extends through the package housing to electrically connect to a gate terminal of the RF transistor amplifier die, and an output leadframe that extends through the package housing to electrically connect to a drain terminal of the RF transistor amplifier die. The output leadframe includes an output pad region, an output lead that extends outside of the package housing, and a first arm that extends from one of the output pad region and the output lead to be adjacent the first capacitor die.

Abstract: A transistor semiconductor die includes a first current terminal, a second current terminal, and a control terminal. A semiconductor structure is between the first current terminal, the second current terminal, and the control terminal and configured such that a resistance between the first current terminal and the second current terminal is based on a control signal provided at the control terminal. Short circuit protection circuitry is coupled between the control terminal and the second current terminal. In a normal mode of operation, the short circuit protection circuitry is configured to provide a voltage drop that is greater than a voltage of the control signal. In a short circuit protection mode of operation, the short circuit protection circuitry is configured to provide a voltage drop that is less than a voltage of the control signal.

Abstract: A semiconductor device includes a semiconductor layer structure that comprises silicon carbide, a gate dielectric layer on the semiconductor layer structure, the gate dielectric layer including a base gate dielectric layer that is on the semiconductor layer structure and a capping gate dielectric layer on the base gate dielectric layer opposite the semiconductor layer structure, and a gate electrode on the gate dielectric layer opposite the semiconductor layer structure. A dielectric constant of the capping gate dielectric layer is higher than a dielectric constant of the base gate dielectric layer.

Abstract: A semiconductor device includes a semiconductor layer structure of a wide band-gap semiconductor material. The semiconductor layer structure includes a drift region having a first conductivity type and a well region having a second conductivity type. A plurality of segmented gate trenches extend in a first direction in the semiconductor layer structure. The segmented gate trenches include respective gate trench segments that are spaced apart from each other in the first direction with intervening regions of the semiconductor layer structure therebetween. Related devices and fabrication methods are also discussed.

Abstract: RF transistor amplifiers include an RF transistor amplifier die having a Group III nitride-based semiconductor layer structure and a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal that are each on an upper surface of the semiconductor layer structure, an interconnect structure on an upper surface of the RF transistor amplifier die, and a coupling element between the RF transistor amplifier die and the interconnect structure that electrically connects the gate terminals, the drain terminals and the source terminal to the interconnect structure.

Abstract: Inductance-capacitance (LC) resonators having different resonant frequencies, and radio frequency (RF) transistor amplifiers including the same. One usage of such LC resonators is to implement RF short/DC block circuits. A RF transistor amplifier may include a transistor on a base of the RF transistor amplifier coupled to an input and an output of the RF transistor amplifier; a first inductance-capacitance (LC) resonator comprising a first inductance and a first capacitance; and a second LC resonator comprising a second inductance and a second capacitance. The first LC resonator may be configured to resonate at a first frequency, and the second LC resonator may be configured to resonate at a second frequency different from the first frequency.

Abstract: Silicon carbide (SiC) wafers, SiC boules, and related methods are disclosed that provide improved dislocation distributions. SiC boules are provided that demonstrate reduced dislocation densities and improved dislocation uniformity across longer boule lengths. Corresponding SiC wafers include reduced total dislocation density (TDD) values and improved TDD radial uniformity. Growth conditions for SiC crystalline materials include providing source materials in oversaturated quantities where amounts of the source materials present during growth are significantly higher than what would typically be required. Such SiC crystalline materials and related methods are suitable for providing large diameter SiC boules and corresponding SiC wafers with improved crystalline quality.

Abstract: A transistor device includes a semiconductor layer, a surface dielectric layer on the semiconductor layer, and at least a portion of a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced apart from the gate. The transistor device includes an interlayer dielectric layer on the surface dielectric layer, and a field plate on the interlayer dielectric layer. The field plate is laterally spaced apart from the gate, and at least a portion of the field plate includes a recessed portion above the aperture in the surface dielectric layer.