Abstract: A package mold according to some embodiments includes a first mold body and a second mold body, a mold cavity in the first mold body, a gate in a first side of the mold cavity for supplying liquid mold compound into the mold cavity, a longitudinal vent for releasing gas from the mold cavity in a second side of the mold cavity opposite the first side of the mold cavity, and a transverse vent for releasing gas from the mold cavity in a third side of the mold cavity that extends between the first and second sides of the mold cavity. Methods of packaging an electronic device using the package mold and resulting packaged devices are also disclosed.

Abstract: A power component configured to improve partial discharge performance includes at least one terminal that includes a first planar surface, a second planar surface opposite the first planar surface, and a curved surface extending from the first planar surface to the second planar surface. The power component may include at least one of the following: a power module or a bus bar.

Abstract: Semiconductor devices and methods of forming a semiconductor device that includes a deep shielding pattern that may improve a reliability and/or a functioning of the device. An example method may include forming a wide band-gap semiconductor layer structure on a substrate, the semiconductor layer structure including a drift region that has a first conductivity type; forming a plurality of gate trenches in an upper portion of the semiconductor layer structure, the gate trenches spaced apart from each other, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; forming an obstruction over a portion of each gate trench that partially obscures the upper opening; and implanting dopants having a second conductivity type that is opposite the first conductivity type into the bottom surfaces of the gate trenches, where the dopants implanted into the bottom surface of the gate trenches form deep shielding patterns.

Abstract: Power switching devices include a semiconductor layer structure, a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor including a gate finger that has a longitudinal axis that extends in a first direction on the semiconductor layer structure, the gate fingers spaced apart from each other along a second direction, and a gate connector having a longitudinal axis that extends in the second direction, the gate connector connected to the gate fingers of the plurality of unit cell transistors.

Abstract: A power module includes at least one electrically conductive power substrate; and a plurality of power devices arranged on and connected to the at least one electrically conductive power substrate. The power module further includes at least one elevated signal element electrically connected to the plurality of power devices and/or at least one elevated power plane electrically connected to the at least one electrically conductive power substrate and electrically connected to the plurality of power devices.

Abstract: A vertical semiconductor device includes one or more of a substrate, a buffer layer over the substrate, one or more drift layers over the buffer layer, and a spreading layer over the one or more drift layers.

Abstract: A power semiconductor device comprises a semiconductor layer structure comprising a drift region that comprises a wide band-gap semiconductor material that has a first conductivity type, a well region that has a second conductivity type, and a source region that has the first conductivity type in an upper portion of the well region and a gate trench in an upper portion of the semiconductor layer structure and comprising a portion obliquely angled in plan view. Sidewalls of the gate trench may extend along substantially the same crystal plane in the semiconductor layer structure.

Abstract: Shielding techniques are used to provide an embedded sensor element such as a temperature sensing element on a wide bandgap power semiconductor device. A semiconductor device may include a drift layer and an embedded sensor element. The drift layer may be a wide bandgap semiconductor material. A shielding structure is provided in the drift layer below the embedded sensor element. The embedded sensor element may be provided between contacts that are in electrical contact with the shielding well. The distance between the contacts may be minimized. A noise reduction well may be provided between the contacts to further isolate the embedded sensor element from parasitic signals.

Abstract: A transistor semiconductor die includes a drift layer, a first dielectric layer, a first metallization layer, a second dielectric layer, a second metallization layer, a first plurality of electrodes, and a second plurality of electrodes. The first dielectric layer is over the drift layer. The first metallization layer is over the first dielectric layer such that at least a portion of the first metallization layer provides a first contact pad. The second dielectric layer is over the first metallization layer. The second metallization layer is over the second dielectric layer such that at least a portion of the second metallization layer provides a second contact pad and the second metallization layer at least partially overlaps the first metallization layer. The transistor semiconductor die is configured to selectively conduct current between the first contact pad and a third contact pad based on signals provided at the second contact pad.

Abstract: A semiconductor device package includes a package substrate having a die attach region, a silicon carbide (SiC) substrate having a first surface including a semiconductor device layer thereon and a second surface that is opposite the first surface, and a die attach metal stack. The die attach metal stack includes a sputtered die attach material layer that attaches the second surface of the SiC substrate to the die attach region of the package substrate, where the sputtered die attach material layer comprises a void percent of about 15% or less. The sputtered die attach material layer may be formed using a sputter gas including at least one of krypton (Kr), xenon (Xe), or radon (Rn). The die attach metal stack may further include a metal interlayer that prevent contacts with a first barrier metal layer during a phase transition of the die attach material layer.

Abstract: A power converter module includes an active metal braze (AMB) substrate, power converter circuitry, and a housing. The AMB substrate includes an aluminum nitride base layer, a first conductive layer on a first surface of the aluminum nitride base layer, and a second conductive layer on a second surface of the aluminum nitride base layer opposite the first surface. The power converter circuitry includes a number of silicon carbide switching components coupled to one another via the first conductive layer. The housing is over the power converter circuitry and the AMB substrate. By using an AMB substrate with an aluminum nitride base layer, the thermal dissipation characteristics of the power converter module may be substantially improved while maintaining the structural integrity of the power converter module.

Abstract: Nondestructive characterization of crystalline wafers is provided, including defect detection, identification, and counting. Certain aspects relate to development of nondestructive, high fidelity defect characterization and/or dislocation counting methods based on deep neural networks. Certain aspects relate to nondestructive methods for defect characterization of silicon carbide (SiC) wafers. By subjecting SiC wafers to nondestructive defect characterization, SiC wafers in their final state may be characterized and subsequently used for device fabrication, vastly reducing the expense of the characterization process. Nondestructive defect characterization also allows for increased sampling and improved feedback loops between crystalline growth process development and subsequent device production.

Abstract: Silicon carbide (SiC) crystalline materials and related methods are disclosed that provide SiC crystalline materials with reduced optical absorption. In certain aspects, SiC crystalline materials with reduced absorption coefficients for wavelengths of light within the visible spectrum are disclosed. Various peaks in absorption over a wavelength spectrum may be reduced in SiC crystalline materials to improve overall absorption coefficient uniformity across the visible spectrum. By providing such improvements in absorption coefficients for SiC crystalline materials, reduced reflection and transmission losses of light in corresponding devices may be realized. Related methods are disclosed that include various combinations of crystalline growth, with and without various post-growth thermal conditioning steps.

Abstract: The disclosure is directed to a power module that includes at least one power substrate, a housing arranged on the at least one power substrate, and a first terminal electrically connected to the at least one power substrate. The first terminal includes a contact surface located above the housing at a first elevation. The power module includes a second terminal including a contact surface located above the housing at a second elevation different from the first elevation, a third terminal electrically connected to the at least one power substrate, and a plurality of power devices electrically connected to the at least one power substrate.

Abstract: A semiconductor device includes a vertical transistor and a body diode. Various improvements to the semiconductor device allow for improved performance of the body diode, in particular to reduced snappiness and increased softness.

Abstract: Power semiconductor devices, and more particularly arrangements of power semiconductor devices for improved thermal performance in high power applications are disclosed. Arrangements for multiple power semiconductor devices within a package and/or module are provided that more efficiently utilize the active device area of each power semiconductor device for a given operational specification. Certain arrangements are provided that reduce the effects of thermal crowding in order to provide increased power capability or a similar power capability in a reduced device size. Improved thermal balancing may be provided by variable spacing and/or variable offset distances between next-adjacent power semiconductor devices. In this manner, active areas of power devices and/or modules may include an increased density of power semiconductor devices within a given area while also exhibiting improved thermal profiles during operation, thereby providing improved operating characteristics and/or increased operating lifetimes.

Abstract: A transistor package that includes a metal submount; a transistor die mounted on said metal submount; a surface mount IPD component that includes a dielectric substrate; and the dielectric substrate mounted on said metal submount. Additionally, the dielectric substrate includes one of the following: an irregular shape, a non-square shape, and a nonrectangular shape.

Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.