Abstract: A semiconductor device includes a semiconductor layer structure that comprises silicon carbide, a gate dielectric layer on the semiconductor layer structure, the gate dielectric layer including a base gate dielectric layer that is on the semiconductor layer structure and a capping gate dielectric layer on the base gate dielectric layer opposite the semiconductor layer structure, and a gate electrode on the gate dielectric layer opposite the semiconductor layer structure. A dielectric constant of the capping gate dielectric layer is higher than a dielectric constant of the base gate dielectric layer.
Abstract: An apparatus includes a substrate; a group III-Nitride barrier layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; a p-region being arranged at or below the group III-Nitride barrier layer; and a recovery enhancement circuit configured to reduce an impact of an overload received by the gate. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain.
Type:
Grant
Filed:
May 17, 2021
Date of Patent:
March 12, 2024
Assignee:
Wolfspeed, Inc.
Inventors:
Thomas J. Smith, Jr., Saptharishi Sriram, Charles W. Richards, IV
Abstract: A packaged semiconductor device includes a first bond pad, a second bond pad, a first bond wire that includes a first end bonded to the first bond pad and a second end bonded to the second bond pad, and a second bond wire that includes a first end that is electrically connected to the first bond pad and a second end that is electrically connected to the second bond pad. The first end of the second bond wire is bonded to the first end of the first bond wire. A method of bonding a bond wire includes bonding a first end of a first bond wire to a contact surface of a first bond pad and bonding a first end of a second bond wire to a surface of the first end of the first bond wire.
Abstract: A precursor for a vertical semiconductor device is provided with a substrate, a drift region over the substrate, and an upper precursor region over the drift region. The top surface of the precursor is substantially planar, and the substrate and the drift region are doped with a first dopant of a first polarity. In a first embodiment, a series of implants with a second dopant is provided in the upper precursor region via the top surface to form each of at least two gate regions such that each implant of the series of implants is provided at a different depth below the top surface. In a second embodiment, a series of implants with the first dopant is provided in the upper precursor region via the top surface to form a channel region that has at least a portion between two gate regions.
Type:
Grant
Filed:
September 22, 2021
Date of Patent:
February 6, 2024
Assignee:
Wolfspeed, Inc.
Inventors:
Daniel Jenner Lichtenwalner, Sei-Hyung Ryu, Arman Ur Rashid
Abstract: A package for power electronics includes a power substrate, a number of power semiconductor die, and a Kelvin connection contact. Each one of the power semiconductor die are on the power substrate and include a first power switching pad, a second power switching pad, a control pad, a semiconductor structure, and a Kelvin connection pad. The semiconductor structure is between the first power switching pad, the second power switching pad, and the control pad, and is configured such that a resistance of a power switching path between the first power switching pad and the second power switching pad is based on a control signal provided at the control pad. The Kelvin connection pad is coupled to the power switching path. The Kelvin connection contact is coupled to the Kelvin connection pad of each one of the power semiconductor die via a Kelvin conductive trace on the power substrate.
Type:
Grant
Filed:
June 21, 2021
Date of Patent:
January 30, 2024
Assignee:
Wolfspeed, Inc.
Inventors:
Brice McPherson, Daniel Martin, Jennifer Stabach
Abstract: A power converter module includes an active metal braze (AMB) substrate, power converter circuitry, and a housing. The AMB substrate includes an aluminum nitride base layer, a first conductive layer on a first surface of the aluminum nitride base layer, and a second conductive layer on a second surface of the aluminum nitride base layer opposite the first surface. The power converter circuitry includes a number of silicon carbide switching components coupled to one another via the first conductive layer. The housing is over the power converter circuitry and the AMB substrate. By using an AMB substrate with an aluminum nitride base layer, the thermal dissipation characteristics of the power converter module may be substantially improved while maintaining the structural integrity of the power converter module.
Type:
Grant
Filed:
April 17, 2020
Date of Patent:
January 30, 2024
Assignee:
Wolfspeed, Inc.
Inventors:
Mrinal K. Das, Adam Barkley, Henry Lin, Marcelo Schupbach
Abstract: A radio frequency (RF) power amplifier device package includes a substrate and a first die attached to the substrate at a bottom surface of the first die. The first die includes top gate or drain contacts on a top surface of the first die opposite the bottom surface. At least one of the top gate or drain contacts is electrically connected to a respective bottom gate or drain contact on the bottom surface of the first die by a respective conductive via structure. An integrated interconnect structure, which is on the first die opposite the substrate, includes a first contact pad on the top gate contact or the top drain contact of the first die, and at least one second contact pad connected to a package lead, a contact of a second die, impedance matching circuitry, and/or harmonic termination circuitry.
Type:
Grant
Filed:
March 24, 2021
Date of Patent:
January 23, 2024
Assignee:
Wolfspeed, Inc.
Inventors:
Basim Noori, Marvin Marbell, Kwangmo Chris Lim, Qianli Mu
Abstract: A transistor device includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher bandgap than the channel layer. A modified access region is provided at an upper surface of the barrier layer opposite the channel layer. The modified access region includes a material having a lower surface barrier height than the barrier layer. A source contact and a drain contact are formed on the barrier layer, and a gate contact is formed between source contact and the drain contact.
Type:
Grant
Filed:
May 20, 2021
Date of Patent:
January 9, 2024
Assignee:
Wolfspeed, Inc.
Inventors:
Kyoung-Keun Lee, Fabian Radulescu, Scott Sheppard
Abstract: Strategic placement and patterning of electrodes, vias, and metal runners can significantly reduce strain in a power semiconductor die. By modifying the path defining electrodes, vias, and metal runners, as well as patterning the material layers thereof, strain can be better managed to increase reliability of a power semiconductor die.
Type:
Grant
Filed:
February 17, 2021
Date of Patent:
January 9, 2024
Assignee:
Wolfspeed, Inc.
Inventors:
Daniel Jenner Lichtenwalner, Edward Robert Van Brunt, Thomas E. Harrington, III, Shadi Sabri, Brett Hull, Brice McPherson, Joe W. McPherson
Abstract: An apparatus includes a substrate. The apparatus further includes a group III-nitride buffer layer on the substrate; a group III-nitride barrier layer on the group III-nitride buffer layer, the group III-nitride barrier layer including a higher bandgap than a bandgap of the group III-nitride buffer layer. The apparatus further includes a source electrically coupled to the group III-nitride barrier layer; a gate electrically coupled to the group III-nitride barrier layer; a drain electrically coupled to the group III-nitride barrier layer; and a p-region being at least one of the following: in the substrate or on the substrate below said group III-nitride barrier layer.
Type:
Grant
Filed:
December 16, 2020
Date of Patent:
January 2, 2024
Assignee:
Wolfspeed, Inc.
Inventors:
Saptharishi Sriram, Thomas Smith, Alexander Suvorov, Christer Hallin
Abstract: RF transistor amplifiers include a Group III nitride-based RF transistor amplifier die that includes a semiconductor layer structure, a conductive source via that is connected to a source region of the Group III nitride-based RF transistor amplifier die, the conductive source via extending through the semiconductor layer structure, and an additional conductive via that extends through the semiconductor layer structure. A first end of the additional conductive via is connected to a first external circuit and a second end of the additional conductive via that is opposite the first end is connected to a first matching circuit.
Type:
Grant
Filed:
March 29, 2021
Date of Patent:
January 2, 2024
Assignee:
Wolfspeed, Inc.
Inventors:
Basim Noori, Marvin Marbell, Qianli Mu, Kwangmo Chris Lim, Michael E. Watts, Mario Bokatius, Jangheon Kim
Abstract: An integrated circuit device includes a radio frequency transistor amplifier die having a first surface, a second surface, a semiconductor layer structure that is between the first and second surfaces and includes a plurality of transistor cells adjacent the first surface, and terminals coupled to the transistor cells. At least one passive electronic component is provided on the second surface of the die and is electrically connected to at least one of the terminals, for example, by at least one conductive via. One or more conductive pillar structures may protrude from the first surface of the die to provide electrical connections to one or more of the terminals.
Type:
Grant
Filed:
March 21, 2022
Date of Patent:
December 12, 2023
Assignee:
Wolfspeed, Inc.
Inventors:
Terry Alcorn, Daniel Namishia, Fabian Radulescu
Abstract: A transistor device includes a substrate, a semiconductor structure on the substrate, a metallization layer comprising a non-planar surface on a surface of the semiconductor structure, a non-planar encapsulation layer on the non-planar surface of the metallization layer, the non-planar encapsulation layer comprising a non-planar encapsulant surface that is opposite the non-planar surface, and a self-planarizing encapsulation layer on the non-planar encapsulation layer and comprising a planarized surface that is opposite the non-planar encapsulant surface.
Type:
Grant
Filed:
July 30, 2021
Date of Patent:
December 12, 2023
Assignee:
Wolfspeed, Inc.
Inventors:
Chris Hardiman, Daniel Namishia, Kyle Bothe, Elizabeth Keenan
Abstract: A power semiconductor device has a semiconductor layer structure that includes a silicon carbide drift region having a first conductivity type, first and second wells in the silicon carbide drift region that are doped with dopants having a second conductivity type, and a JFET region between the first and second wells. The first and second wells each include a main well and a side well that is between the main well and the JFET region, and each side well includes a respective channel region. A doping concentration of the JFET region exceeds a doping concentration of the silicon carbide drift region, and a minimum width of an upper portion of the JFET region is greater than a minimum width of a lower portion of the JFET region.
Type:
Grant
Filed:
August 27, 2020
Date of Patent:
December 12, 2023
Assignee:
Wolfspeed, Inc.
Inventors:
Kijeong Han, Joohyung Kim, Sei-Hyung Ryu
Abstract: RF amplifiers are provided that include an interconnection structure and a Group III nitride-based RF amplifier die that is mounted on top of the interconnection structure. The Group III nitride-based RF amplifier die includes a semiconductor layer structure. A plurality of unit cell transistors are provided in an upper portion of the semiconductor layer structure, and a gate terminal, a drain terminal and a source terminal are provided on a lower surface of the semiconductor layer structure that is adjacent the interconnection structure.
Type:
Grant
Filed:
March 24, 2021
Date of Patent:
December 5, 2023
Assignee:
Wolfspeed, Inc.
Inventors:
Michael E. Watts, Mario Bokatius, Jangheon Kim, Basim Noori, Qianli Mu, Kwangmo Chris Lim, Marvin Marbell
Abstract: Semiconductor devices include a semiconductor layer structure comprising a drift region that includes a wide band-gap semiconductor material. A shielding pattern is provided in an upper portion of the drift region in an active region of the device and a termination structure is provided in the upper portion of the drift region in a termination region of the device. A gate trench extends into an upper surface of the semiconductor layer structure. The semiconductor layer structure includes a semiconductor layer that extends above and at least partially covers the termination structure.
Type:
Grant
Filed:
November 19, 2020
Date of Patent:
December 5, 2023
Assignee:
Wolfspeed, Inc.
Inventors:
Daniel J. Lichtenwalner, Edward R. Van Brunt, Brett Hull
Abstract: A power semiconductor device comprises a semiconductor layer structure having a wide band-gap drift region having a first conductivity type, a gate trench having first and second opposed sidewalls that extend in a first direction in an upper portion of the semiconductor layer structure, first and second well regions having a second conductivity type in the upper portion of the semiconductor layer structure, the first well region comprising part of the first sidewall and the second well region comprising part of the second sidewall. A deep shielding region having the second conductivity type is provided underneath the gate trench, and a plurality of deep shielding connection patterns that have the second conductivity type are provided that electrically connect the deep shielding region to the first and second well regions. The deep shielding connection patterns are spaced apart from each other along the first direction.
Type:
Grant
Filed:
February 15, 2023
Date of Patent:
December 5, 2023
Assignee:
Wolfspeed, Inc.
Inventors:
Naeem Islam, Woongsun Kim, Daniel J. Lichtenwalner, Sei-Hyung Ryu
Abstract: RF transistor amplifiers an RF transistor amplifier die having a semiconductor layer structure, an interconnect structure having first and second opposing sides, wherein the first side of the interconnect structure is adjacent a surface of the RF transistor amplifier die such that the interconnect structure and the RF transistor amplifier die are in a stacked arrangement, and one or more circuit elements on the first and/or second side of the interconnect structure.
Type:
Grant
Filed:
September 11, 2020
Date of Patent:
December 5, 2023
Assignee:
Wolfspeed, Inc.
Inventors:
Basim Noori, Marvin Marbell, Scott Sheppard, Kwangmo Chris Lim, Alexander Komposch, Qianli Mu
Abstract: Power semiconductor devices comprise a gate pad, a plurality of gate fingers, and a first gate resistor and a first switch that are coupled between the gate pad and the gate fingers.
Type:
Grant
Filed:
July 22, 2021
Date of Patent:
November 7, 2023
Assignee:
Wolfspeed, Inc.
Inventors:
In-Hwan Ji, Jae-Hyung Park, Edward Van Brunt
Abstract: Semiconductor devices include a silicon carbide drift region having an upper portion and a lower portion. A first contact is on the upper portion of the drift region and a second contact is on the lower portion of the drift region. The drift region includes a superjunction structure that includes a p-n junction that is formed at an angle of between 10° and 30° from a plane that is normal to a top surface of the drift region. The p-n junction extends within +/?1.5° of a crystallographic axis of the silicon carbide material forming the drift region.
Type:
Grant
Filed:
July 9, 2021
Date of Patent:
October 17, 2023
Assignee:
Wolfspeed, Inc.
Inventors:
Edward Robert Van Brunt, Alexander V. Suvorov, Vipindas Pala, Daniel J. Lichtenwalner, Qingchun Zhang