Abstract: A package for power electronics includes a power substrate, a number of power semiconductor die, and a Kelvin connection contact. Each one of the power semiconductor die are on the power substrate and include a first power switching pad, a second power switching pad, a control pad, a semiconductor structure, and a Kelvin connection pad. The semiconductor structure is between the first power switching pad, the second power switching pad, and the control pad, and is configured such that a resistance of a power switching path between the first power switching pad and the second power switching pad is based on a control signal provided at the control pad. The Kelvin connection pad is coupled to the power switching path. The Kelvin connection contact is coupled to the Kelvin connection pad of each one of the power semiconductor die via a Kelvin conductive trace on the power substrate.

Abstract: A transistor device includes a semiconductor layer, source and drain contacts on the semiconductor layer, a gate contact on the semiconductor layer between the source and drain contacts, and a field plate over the semiconductor layer between the gate contact and the drain contact. The transistor device includes a first electrical connection between the field plate and the source contact that is outside an active region of the transistor device, and a second electrical connection between the field plate and the source contact.

Abstract: A device binning and/or matching process includes measuring with a testing device currents and/or voltages of a device with respect to time, determining with the testing device binning and/or matching criteria for the device based on transfer data generated from the device currents and/or the voltages measured with respect to time, and outputting with the testing device the binning and/or matching criteria for the device. A system and power module are also disclosed.

Abstract: A multi-cell transistor includes a semiconductor structure, a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure, wherein the unit cell transistors are spaced apart from each other along a second direction, and an isolation structure that is positioned between a first group of the unit cell transistors and a second group of the unit cell transistors and that extends above the semiconductor structure.

Abstract: A method of packaging a radio frequency (RF) transistor device includes attaching one or more electronic devices to a carrier substrate, applying an encapsulant over at least one of the one or more electronic devices, and providing a protective structure on the carrier substrate over the one or more electronic devices. A packaged RF transistor device includes a carrier substrate, one or more electronic devices attached to the carrier substrate, an encapsulant material over at least one of the one or more electronic devices and extending onto the carrier substrate, and a protective structure on the carrier substrate over the one or more electronic devices and the encapsulant material.

Abstract: A semiconductor device configured for a radio frequency (RF) application and further configured for passive device integration and/or improved cooling includes a substrate; an active region portion arranged on the substrate, the active region portion includes at least one radio frequency (RF) transistor amplifier; a cavity arranged within the substrate; and one or more radio frequency (RF) devices arranged in the cavity.

Abstract: The present disclosure relates to a power module comprising a substrate, first and second pluralities of vertical power devices, and first and second terminal assemblies. The substrate has a top surface with a first trace and a second trace. The first plurality of vertical power devices and a second plurality of vertical power devices are electrically coupled to form part of a power circuit. The first plurality of vertical power devices are electrically and mechanically directly coupled between the first trace and a bottom of a first elongated bar of the first terminal assembly. The second plurality of vertical power devices are electrically and mechanically directly coupled between the second trace and a bottom of a second elongated bar of the second terminal assembly.

Abstract: A semiconductor device includes a semiconductor layer structure comprising a source/drain region, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer. The source/drain region comprises a first portion comprising a first dopant concentration and a second portion comprising a second dopant concentration. The second portion is closer to a center of the gate electrode than the first portion.

Abstract: The present disclosure describes a power module having a substrate, first and second pluralities of vertical power devices, and first and second terminal assemblies. The substrate has a top surface with a first trace and a second trace. The first plurality of vertical power devices and the second plurality of vertical power devices are electrically coupled to form part of a power circuit. The first plurality of vertical power devices is electrically and mechanically directly coupled between the first trace and a bottom of a first elongated bar of the first terminal assembly. The second plurality of vertical power devices are electrically and mechanically directly coupled between the second trace and a bottom of a second elongated bar of the second terminal assembly.

Abstract: Fabrication of a bondwire inductor between connection pads of a semiconductor package using a wire bonding process is disclosed herein. To that end, the bondwire inductor is fabricated by extending a bondwire connecting two connection pads of the semiconductor package around a dielectric structure, e.g., a dielectric post or posts, disposed between the connection pads a defined amount. In so doing, the bondwire inductor adds inductance between the connection pads, where the added inductance is defined by factors which at least include the amount the bondwire extends around the dielectric structure. Such additional inductance may be particularly beneficial for certain semiconductor devices and/or circuits, e.g., monolithic microwave integrated circuits (MMICs) to control or supplement impedance matching, harmonic termination, matching biasing, etc.

Abstract: A power module including at least one substrate, a housing arranged on the at least one power substrate, a first terminal electrically connected to the at least one power substrate, a second terminal including a contact surface, a third terminal electrically connected to the at least one power substrate, a plurality of power devices arranged on and connected to the at least one power substrate, and the third terminal being electrically connected to at least one of the plurality of power devices. The power module further including a base plate and a plurality of pin fins arranged on the base plate and the plurality of pin fins configured to provide direct cooling for the power module.

Abstract: An RF transistor package includes a metal submount; a transistor die mounted to the metal submount; and a surface mount IPD component mounted to the metal submount. The surface mount IPD component includes a dielectric substrate that includes a top surface and a bottom surface and at least a first pad and a second pad arranged on a top surface of the surface mount IPD component; at least one surface mount device includes a first terminal and a second terminal, the first terminal of the surface mount device mounted to the first pad and the second terminal mounted to the second pad; at least one of the first terminal and the second terminal being configured to be isolated from the metal submount by the dielectric substrate; and at least one wire bond bonded to the at least one of the first pad and the second pad.

Abstract: A semiconductor device includes a semiconductor layer structure, a gate insulating pattern on the semiconductor layer structure, a gate electrode on the gate insulating pattern, and an interface layer between the gate insulating pattern and the semiconductor layer structure, the interface layer having a first segment and a second segment with a gap therebetween.

Abstract: A packaged electronic circuit includes a substrate having an upper surface, a first metal layer on the upper surface of the substrate, a first polymer layer on the first metal layer opposite the substrate, a second metal layer on the first polymer layer opposite the first metal layer, a dielectric layer on the first polymer layer and at least a portion of the second metal layer and a second polymer layer on the dielectric layer.

Abstract: RF transistor amplifiers are provided that include a submount and an RF transistor amplifier die that is mounted on top of the submount. A multi-layer encapsulation is formed that at least partially covers the RF transistor amplifier die. The multi-layer encapsulation includes a first dielectric layer and a first conductive layer, where the first dielectric layer is between a top surface of the RF transistor amplifier die and the first conductive layer.

Abstract: A transistor amplifier includes a group III-nitride based amplifier die including a gate terminal, a drain terminal, and a source terminal on a first surface of the amplifier die and an interconnect structure electrically bonded to the gate terminal, drain terminal and source terminal of the amplifier die on the first surface of the amplifier die and electrically bonded to an input path and output path of the transistor amplifier.

Abstract: A semiconductor device includes a semiconductor layer structure and a gate formed in a gate trench in the semiconductor layer structure. The gate trench has a bottom surface comprising a first portion at a first level and a second portion at a second level, different from the first level. A method of forming a semiconductor device includes providing a semiconductor layer structure, etching a first gate trench into the semiconductor layer structure, etching a second gate trench into the semiconductor layer structure, and performing an ion implantation into a bottom surface of the second gate trench. The second gate trench is deeper than the first gate trench, and at least a portion of the second gate trench is connected to the first gate trench.

Abstract: Semiconductor devices, and in particular semiconductor devices for improved resistance measurements and related methods are disclosed. Contact structures for semiconductor devices are disclosed that provide access to resistance measurements with reduced influence of testing-related resistances, thereby improving testing accuracy, particularly for semiconductor devices with low on-resistance ratings. A semiconductor device may include an active region and an inactive region that is arranged along a perimeter of the active region. The semiconductor device may be arranged with a topside contact to provide access for resistance measurements, for example Kelvin-sensing resistance measurements. Related methods include performing resistance measurements from a topside of the semiconductor device, even when the active region of the semiconductor device forms a vertical contact structure.

Abstract: A field effect transistor comprising a buffer and channel layer formed successively on a substrate. A source electrode, drain electrode, and gate are all formed in electrical contact with the channel layer, with the gate between the source and drain electrodes. A spacer layer is formed on at least a portion of a surface of the channel layer between the gate and drain electrode and a field plate is formed on the spacer layer isolated from the gate and channel layer. The spacer layer is electrically connected by at least one conductive path to the source electrode, wherein the field plate reduces the peak operating electric field in the device.

Abstract: Power semiconductor devices include a semiconductor layer structure comprising an active area with a plurality of unit cell transistors and an inactive gate pad area, a gate resistor layer on an upper side of the semiconductor layer structure, an inner contact that is directly on the upper side of the gate resistor layer, and an outer contact that is directly on the upper side of the gate resistor layer. The outer contact encloses the inner contact within the inactive gate pad area of the semiconductor device.