Patents Assigned to Wolfspeed, Inc.
  • Patent number: 11522504
    Abstract: Inductance-capacitance (LC) resonators having different resonant frequencies, and radio frequency (RF) transistor amplifiers including the same. One usage of such LC resonators is to implement RF short/DC block circuits. A RF transistor amplifier may include a transistor on a base of the RF transistor amplifier coupled to an input and an output of the RF transistor amplifier; a first inductance-capacitance (LC) resonator comprising a first inductance and a first capacitance; and a second LC resonator comprising a second inductance and a second capacitance. The first LC resonator may be configured to resonate at a first frequency, and the second LC resonator may be configured to resonate at a second frequency different from the first frequency.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: December 6, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Haedong Jang, Madhu Chidurala, Richard Wilson
  • Patent number: 11519098
    Abstract: Silicon carbide (SiC) wafers, SiC boules, and related methods are disclosed that provide improved dislocation distributions. SiC boules are provided that demonstrate reduced dislocation densities and improved dislocation uniformity across longer boule lengths. Corresponding SiC wafers include reduced total dislocation density (TDD) values and improved TDD radial uniformity. Growth conditions for SiC crystalline materials include providing source materials in oversaturated quantities where amounts of the source materials present during growth are significantly higher than what would typically be required. Such SiC crystalline materials and related methods are suitable for providing large diameter SiC boules and corresponding SiC wafers with improved crystalline quality.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: December 6, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Yuri Khlebnikov, Robert T. Leonard, Elif Balkas, Steven Griffiths, Valeri Tsvetkov, Michael Paisley
  • Patent number: 11502178
    Abstract: A transistor device includes a semiconductor layer, a surface dielectric layer on the semiconductor layer, and at least a portion of a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced apart from the gate. The transistor device includes an interlayer dielectric layer on the surface dielectric layer, and a field plate on the interlayer dielectric layer. The field plate is laterally spaced apart from the gate, and at least a portion of the field plate includes a recessed portion above the aperture in the surface dielectric layer.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: November 15, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Kyle Bothe, Jia Guo, Terry Alcorn, Fabian Radulescu, Scott Sheppard
  • Patent number: 11437362
    Abstract: A multi-cavity package includes a single metal flange having first and second opposing main surfaces. The multi-cavity package also includes a circuit board attached to the first main surface of the single metal flange. The circuit board includes a first surface facing the single metal flange, and a second surface facing away from the first surface. The circuit board also includes a plurality of openings exposing different regions of the first main surface of the single metal flange. The circuit board also includes a lateral extension that overhangs the single metal flange. A corresponding method of manufacturing is also provided.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: September 6, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Saurabh Goel, Alexander Komposch, Cynthia Blair, Cristian Gozzi
  • Patent number: 11424333
    Abstract: Pursuant to some embodiments of the present invention, transistor devices are provided that include a semiconductor structure, a gate finger extending on the semiconductor structure in a first direction, and a gate interconnect extending in the first direction and configured to be coupled to a gate signal at an interior position of the gate interconnect, where the gate interconnect is connected to the gate finger at a position offset from the interior position of the gate interconnect.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: August 23, 2022
    Assignee: WolfSpeed, Inc.
    Inventors: Frank Trang, Zulhazmi Mokhti, Haedong Jang
  • Patent number: 11417746
    Abstract: A transistor device includes a gate finger and a drain finger extending on a semiconductor structure, a gate bond pad coupled to the gate finger, and a drain bond pad coupled to the drain finger. The gate bond pad extends on the gate finger and/or the drain bond pad extends on the drain finger.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: August 16, 2022
    Assignee: WolfSpeed, Inc.
    Inventors: Frank Trang, Zulhazmi Mokhti, Haedong Jang
  • Patent number: 11417617
    Abstract: Packaged transistor devices are provided that include a transistor on a base of the packaged transistor device, the transistor comprising a control terminal and an output terminal, a first bond wire electrically coupled between an input lead and the control terminal of the transistor, a second bond wire electrically coupled between an output lead and the output terminal of the transistor, and an isolation material that is and physically between the first bond wire and the second bond wire, wherein the isolation material is configured to reduce a coupling between the first bond wire and the second bond wire.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: August 16, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Frank Trang, Haedong Jang, Zulhazmi Mokhti
  • Patent number: 11387336
    Abstract: Pursuant to some embodiments of the present invention, transistor devices are provided that include a semiconductor structure, a gate finger extending on the semiconductor structure in a first direction, and a gate interconnect extending in the first direction and configured to be coupled to a gate signal at an interior position of the gate interconnect, where the gate interconnect is connected to the gate finger at a position offset from the interior position of the gate interconnect.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: July 12, 2022
    Assignee: WolfSpeed, Inc.
    Inventors: Frank Trang, Zulhazmi Mokhti, Haedong Jang
  • Patent number: 11387340
    Abstract: A transistor device includes a gate finger and a drain finger extending on a semiconductor structure, a gate bond pad coupled to the gate finger, and a drain bond pad coupled to the drain finger. The gate bond pad extends on the gate finger and/or the drain bond pad extends on the drain finger.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: July 12, 2022
    Assignee: WolfSpeed, Inc.
    Inventors: Frank Trang, Zulhazmi Mokhti, Haedong Jang
  • Patent number: 11371163
    Abstract: Stabilized, high-doped silicon carbide is described. A silicon carbide crystal is grown on a substrate using chemical vapor deposition so that the silicon carbide crystal includes a dopant and the strain compensating component. The strain compensating component can be an isoelectronic element and/or an element with the same majority carrier type as the dopant. The silicon carbide crystal can then be cut into silicon carbide wafers. In some embodiments, the dopant is n-type and the strain compensating component is selected from a group comprising germanium, tin, arsenic, phosphorus, and combinations thereof. In some embodiments, the strain compensating component comprises germanium and the dopant is nitrogen.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: June 28, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Adrian Powell, Al Burk, Michael O'Loughlin
  • Patent number: 11367696
    Abstract: RF amplifiers are provided that include a submount such as a thermally conductive flange. A dielectric substrate is mounted on an upper surface of the submount, the dielectric substrate having a first outer sidewall, a second outer sidewall that is opposite and substantially parallel to the first outer sidewall, and an interior opening. An RF amplifier die is mounted on the submount within the interior opening of the dielectric substrate, where a longitudinal axis of the RF amplifier die defines a first axis. The RF amplifier die is positioned so that a first angle defined by the intersection of the first axis with the first outer sidewall is between 5° and 45°. The dielectric substrate may be a ceramic substrate or a dielectric layer of a printed circuit board.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: June 21, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Simon Ward, Richard Wilson, Alexander Komposch
  • Patent number: 11356070
    Abstract: RF transistor amplifiers include an RF transistor amplifier die having a semiconductor layer structure, a coupling element on an upper surface of the semiconductor layer structure, and an interconnect structure on an upper surface of the coupling element so that the RF transistor amplifier die and the interconnect structure are in a stacked arrangement. The coupling element includes a first shielded transmission line structure.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: June 7, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Kwangmo Chris Lim, Basim Noori, Qianli Mu, Marvin Marbell, Scott Sheppard, Alexander Komposch
  • Patent number: 11355600
    Abstract: A high electron mobility transistor includes a channel layer, a barrier layer on the channel layer, source and drain contacts on the barrier layer, a gate contact between the source and drain contacts, and a multi-layer passivation structure on the upper surface of the barrier layer between the source contact and the drain contact. The multi-layer passivation structure includes a first passivation layer that comprises a charge dissipation material directly contacts the upper surface of the barrier layer and a second passivation layer comprising a different material than the first passivation layer that also directly contacts the upper surface of the barrier layer. In some embodiments, at least one recess may be formed in the upper surface of the barrier layer and the second passivation layer may be formed within the recesses.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: June 7, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Kyoung-Keun Lee, Fabian Radulescu, Scott Sheppard
  • Patent number: 11355630
    Abstract: Semiconductor devices and methods of forming a semiconductor device that includes a polysilicon layer that may improve device reliability and/or a functioning of the device. An example device may include a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; and a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: June 7, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Woongsun Kim, Daniel J. Lichtenwalner, Naeem Islam, Sei-Hyung Ryu
  • Patent number: 11336253
    Abstract: An amplifier circuit includes a first port, a second port, a reference potential port, and an RF amplifier device having a first terminal electrically coupled to the first port, a second terminal electrically coupled to the second port, and a reference potential terminal electrically coupled to the reference potential port. The RF amplifier device amplifies an RF signal across an RF frequency range that includes a fundamental RF frequency. An impedance matching network is electrically coupled to the first terminal and the first port. The impedance matching network includes a baseband termination circuit that presents low impedance in a baseband frequency region, a fundamental frequency matching circuit that presents a complex conjugate of an intrinsic impedance of the RF amplifier device in the RF frequency range, and a second order harmonic termination circuit that presents low impedance at second order harmonics of frequencies in the fundamental RF frequency range.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: May 17, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Bayaner Arigong, Haedong Jang, Richard Wilson, Frank Trang, Qianli Mu, E J Hashimoto
  • Patent number: 11316028
    Abstract: Transistors are fabricated by forming a nitride-based semiconductor barrier layer on a nitride-based semiconductor channel layer and forming a protective layer on a gate region of the nitride-based semiconductor barrier layer. Patterned ohmic contact metal regions are formed on the barrier layer and annealed to provide first and second ohmic contacts. The annealing is carried out with the protective layer on the gate region. A gate contact is also formed on the gate region of the barrier layer. Transistors having protective layer in the gate region are also provided as are transistors having a barrier layer with a sheet resistance substantially the same as an as-grown sheet resistance of the barrier layer.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: April 26, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Scott T. Sheppard, Richard Peter Smith, Zoltan Ring
  • Patent number: 11282951
    Abstract: A semiconductor device includes a semiconductor layer structure comprising a source/drain region, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer. The source/drain region comprises a first portion comprising a first dopant concentration and a second portion comprising a second dopant concentration. The second portion is closer to a center of the gate electrode than the first portion.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: March 22, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Philipp Steinmann, Edward Van Brunt, Jae Hyung Park, Vaishno Dasika
  • Patent number: 11276762
    Abstract: A semiconductor device includes a semiconductor layer structure, a gate insulating pattern on the semiconductor layer structure, a gate electrode on the gate insulating pattern, and an interface layer between the gate insulating pattern and the semiconductor layer structure, the interface layer having a first segment and a second segment with a gap therebetween.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: March 15, 2022
    Assignee: Wolfspeed, Inc.
    Inventor: Daniel Jenner Lichtenwalner
  • Patent number: 11244831
    Abstract: A transistor device is provided. The transistor device includes a substrate, a channel layer on the substrate, the channel layer including a GaN material, a barrier layer that is on the channel layer and that includes an AlGaN material, a drain electrode that is on the barrier layer in a drain region of the device, a source ohmic structure that is at least partially recessed into the barrier layer in a source region of the device, a source electrode that is on the source ohmic structure and a gate contact that is on the barrier layer and that is in a gate region of the device that is between the drain region and the source region.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: February 8, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Saptharishi Sriram, Yueying Liu
  • Patent number: D969762
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: November 15, 2022
    Assignee: Wolfspeed, Inc.
    Inventor: Kuldeep Saxena