Abstract: An interconnect array uses repeated application of an interconnect pattern (“tile”). The tile has eight I/O signal pins forming a perimeter array, a central pin that can be either a ground pin or an I/O power pin, and an offset ground pin. The I/O signal pins are associated with the same or multiple I/O banks. If the central pin is an I/O power pin, it is optionally associated with an I/O bank associated with one or more of the I/O signal pins.

Abstract: In one embodiment, a receiver circuit is provided. The receiver circuit includes a low-power equalization circuit having a first linear equalization circuit coupled to receive serial data. The receiver circuit includes a low-noise equalization circuit having a second linear equalization circuit coupled to receive the serial data, and a non-linear equalization circuit coupled to an output of the second linear equalization circuit. The receiver circuit includes a control circuit configured to enable the low-power equalization circuit and disable the low-noise equalization circuit in response to a first state of a control signal. The control circuit is configured to disable the low-power equalization circuit and enable the low-noise equalization circuit in response to a second state of the control signal.

Abstract: In one embodiment, a method is provided for determining a level of resilience of a circuit to single event upsets based on a layout of a circuit design. A set of locations in the layout of the circuit design is selected. A respective maximum level of linear energy transfer (LET) that is tolerable for each location in the selected set is determined. For each determined maximum level of LET, cross-section values at locations having the maximum level of LET are summed to determine a respective total cross-section value for the maximum level of LET. For each determined maximum level of LET, the total cross-section value is divided by the determined maximum level of LET to produce respective intermediate values. The respective intermediate values are summed to determine a level of resilience.

Abstract: Method and apparatus for amplification in an IC are described. A dual mode isolation amplifier having two modes of operation is provided. In the first mode of operation for a resistor-loaded differential transconductance with additional gain, a first switch circuit is placed in a substantially nonconductive state for electrically decoupling from a first current source node and a second current source node. A second switch circuit is placed in a substantially conductive state for electrically coupling a capacitor thereof to the first current source node and the second current source node. At high frequencies, a first resistance associated with the capacitor coupled in parallel with a resistive load is substantially reduced. The resistive load is coupled between the first current source node and the second current source node. The first resistance is reduced by approximating a short circuit by the capacitor during high-frequency operation.

Abstract: A high data rate transceiver for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. The transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.

Abstract: Circuits and methods are provided for estimating a latency through a FIFO buffer. A first detector detects first instances of a pattern in first data values serially written to a write port of the FIFO buffer. A second detector detects second instances of the pattern in second data values serially read from a read port of the FIFO buffer. The second data values are the first data values delayed by the latency through the FIFO buffer. A counter counts a count of active transitions of a sample clock signal. The counter starts on each detected first instance and stops on each detected second instances. The count provides an estimate of the latency of the FIFO buffer.

Abstract: In one embodiment, a method for parallel routing of a circuit design is provided. Placement of a netlist of the circuit design is determined for a target device. A plurality of regions of the target device is defined. Each region of the plurality of regions is assigned to a respective set of processors, each set including at least one processor. Global routing of nets of the netlist on the target device is performed. The global routing of each net restricts the net to one or more possible routes through a corresponding subset of the plurality of regions. Local routing of the netlist is concurrently performed within the plurality of regions using the respective sets of processors. Within each region, the local routing of the netlist is performed exclusively by the respective set of one or more processors.

Abstract: A system for protecting an input/output (I/O) pin of an integrated circuit device (IC) from single event transients is disclosed. The system includes a first delay circuit that is configured to delay a clock signal from the clock source by a first predetermined amount of time, and a second delay circuit that is configured to delay the clock signal by a second predetermined amount of time. The system further includes a first register that is clocked by the clock signal, a second register that is clocked by the clock signal delayed by the first predetermined amount of time, and a third register that is clocked by the clock signal delayed by the second predetermined amount of time. The system also includes voter circuits, where each voter circuit is configured to receive a first data signal from an output of the first register, a second data signal from an output of the second register, and a third data signal from an output of the third register.

Abstract: A semiconductor device includes a substrate having a top surface and a bottom surface, and a through-silicon via (TSV) extending from the top surface of the substrate to the bottom surface of the substrate, the TSV having a height and a side profile extending along a longitudinal axis, wherein the side profile has an upper segment forming a first angle relative to the longitudinal axis, and a lower segment forming a second angle relative to the longitudinal axis, the second angle being different from the first angle, and wherein the lower segment has a height that is less than 20% of the height of the TSV.

Abstract: An interconnect structure includes a substrate, a first diffusion region within the substrate, a plurality of first lines on the substrate and the first diffusion region, a first enclosure coupled to an end of the plurality of first lines, and a first contact within the first enclosure. The interconnect structure further includes a second diffusion region within the substrate, a plurality of second lines on the substrate and the second diffusion region, a second enclosure coupled to an end of the plurality of second lines, and a second contact within the second enclosure. A spacing can be present between the plurality of first lines and the plurality of second lines. The plurality of first lines, the first contact, the plurality of second lines, and the second contact are trimmed, but the first enclosure, the second enclosure, and the spacing are not trimmed.

Abstract: A simulation model is provided for flip-chip BGAs to help engineers determine the effects of IC package components. The simulation model includes a bump model, a package planes model, a package bypass capacitor model, a ball model and a PCB model. The simulation model in particular includes resistors, inductors, capacitors and transmission lines to simulate the electrical interaction between signal conductors, power/ground planes, vias and balls that exist in a flip-chip ball grid array (BGA) package. The simulation model helps engineers understand actual physical effects of flip-chip and IC package interactions, as well as the impact of the effects of power supply droop, ground bounce and crosstalk between adjacent signals, not only on the IC package level, but at the computer system level.

Abstract: A packet processor includes a memory and a programmable compute pipeline. The memory stores microcode that specifies respective sets for the packet types, and the respective set for each type specifies elementary operations for each stage except an initial stage of the programmable compute pipeline. The programmable compute pipeline includes a sequence of stages beginning with the initial stage. The initial stage includes an operation selector that selects the respective set for the type of each packet. Each stage except the initial stage includes elementary components that are programmable to concurrently perform each of multiple combinations of elementary operations. The elementary components concurrently perform a selected one of the combinations for each packet. The selected combination includes the elementary operations specified for the stage in the respective set that the operation selector selects for the packet's type.

Abstract: A circuit for reducing power consumption in input ports of an integrated circuit is disclosed. The circuit comprises a plurality of receiver circuits of the integrated circuit for receiving input signals coupled to the integrated circuit; and a bias current generator coupled to the plurality of receiver circuits, the bias current generator providing a bias voltage for each receiver circuit of the plurality of receiver circuits to mirror the current in the bias current generator in each of the receiver circuits. A method of reducing power consumption in input ports of an integrated circuit is also disclosed.

Abstract: An embodiment of the invention relates to an integrated circuit such as an FPGA wherein a stable unique identifier is produced by reading an intrinsic characteristic of the IC such as a physically unclonable function, and a related method. In one embodiment, a first unique identifier is generated using the intrinsic characteristic and is subdivided into a plurality of first subsets. A second unique identifier is received and subdivided into a plurality of second subsets. The first and second subsets are compared to identify matching subsets to generate the stable unique identifier. Each of the one or more matching subsets includes a particular one of the plurality of first subsets that matches a corresponding one of the plurality of second subsets. The stable unique identifier can be integrated into logic of the IC. Prior to comparing the subsets, the first and second subsets can be transformed with one-way functions.

Abstract: Decoder circuits and methods down-sample the samples that oversample an input signal having a differential Manchester encoding. A first input port receives first, second, and third samples. A second input port receives a state indicating whether a clock transition or a data transition precedes the first, second, and third samples. A third input port receives first, second, and third down-sampled bits. A detector circuit is configured to generate a detection signal indicating a presence of a short pulse within the samples when the state indicates the clock transition and the second and third down-sampled bits are equal and differ from the first down-sampled bit and the third sample. A generator circuit is configured to generate a fourth down-sampled bit that equals the third sample when the detection signal indicates the presence of the short pulse, and that equals the second sample when the detection signal does not indicate the presence.

Abstract: In one embodiment, a cryptographic device is provided. The cryptographic device includes a persistent memory and a decryption control circuit coupled to the persistent memory. The decryption control circuit is configured to receive an encrypted data stream and decrypt a first portion of the encrypted data stream using a first cryptographic key stored in the persistent memory, the first portion including a second cryptographic key. The decryption circuit is configured to decrypt a second portion of the encrypted data stream using the second cryptographic key, the second portion of the encrypted data stream including payload data.

Abstract: An integrated circuit with capacitor structures includes a substrate and a plurality of vias extending from a front surface to a back surface of the substrate. A plurality of transistors is disposed at the front surface of the substrate and has first and second pluralities of electrodes. A patterned metal layer on the front surface of the semiconductor substrate provides first and second networks. The first network couples the first plurality of electrodes to a first via, and the second network couples the second plurality of electrodes to a second via. A dielectric layer separates first and second patterned metal layers on the back surface of the substrate. The first patterned metal layer includes a first metal plate coupled to the first via, and the second patterned metal layer includes a second metal plate coupled to the second via, forming a capacitor with the dielectric layer.

Abstract: Methods and systems estimate a rate of corruption of storage bits in a logic circuit. One or more processors execute instructions that cause the processors to perform the operations that follow. A description is input describing an environment of the logic circuit, and the description of the environment includes a position of the logic circuit. An atomic particle flux density at the logic circuit is estimated as a function of the description of the environment. A specification is input that specifies the storage bits in the logic circuit. The rate of corruption of the storage bits is determined as a function of the atomic particle flux density and a quantification of the storage bits in the logic circuit.

Abstract: Decoder circuits and methods down-sample the samples that oversample an input signal having a differential Manchester encoding. A first input port receives first, second, and third samples. A second input port receives a state indicating whether a clock transition or a data transition precedes the first, second, and third samples. A third input port receives first, second, and third down-sampled bits. A detector circuit is configured to generate a detection signal indicating a presence of a short pulse within the samples when the state indicates the clock transition and the second and third down-sampled bits are equal and differ from the first down-sampled bit and the third sample. A generator circuit is configured to generate a fourth down-sampled bit that equals the third sample when the detection signal indicates the presence of the short pulse, and that equals the second sample when the detection signal does not indicate the presence.

Abstract: An integrated circuit package is described. The integrated circuit package comprises a substrate having a plurality of sides, where each pair of adjacent sides forms a corner; a die coupled to a first surface of the substrate; a lid having a first portion positioned over the die and a plurality of foot portions, each foot portion of the plurality of foot portions being coupled to the first surface of the substrate at a corresponding corner of the substrate, where a side of the integrated circuit package above the substrate and between two associated foot portions has an opening; and a plurality of contact elements coupled to a second surface of the substrate. A method of forming an integrated circuit package is also shown.