Abstract: A method for address acknowledgement is described. A memory controller interface is embedded as part of an embedded core in a host integrated circuit. Access to the memory controller interface is arbitrated with an arbiter. An accept signal is sent from the memory controller interface to the arbiter to indicate whether the memory controller interface is ready to receive a transaction. Access to the memory controller interface is requested by a master device for passing the transaction to a memory controller via the arbiter. The arbiter is a proxy for the memory controller interface responsive to the accept signal being asserted. An acknowledgement signal is sent from the arbiter as a proxy for the memory controller interface responsive to receipt of the transaction and the accept signal being asserted.

Abstract: A programmable integrated circuit (IC) with mirrored interconnect structure. The IC includes a plurality of arrangements, which are horizontally arranged. Each arrangement includes a first logic column, an interconnect column, and a second logic column. Each interconnect column includes programmable interconnect blocks (148), and each of the first and second logic columns includes programmable logic blocks. Each programmable interconnect block provides a plurality of first input and output ports on a first side and a plurality of second input and output ports on a second side. The first ports and the first side of each of the programmable interconnect blocks physically mirror the second ports and the second side of the programmable interconnect block. The ports of the programmable interconnect blocks are coupled to the ports of the programmable logic blocks in the first and second logic columns.

Abstract: An integrated circuit (IC) combines a first IC chip (die) having a first on-chip interconnect structure and a second IC chip having a second on-chip interconnect structure on a reconstructed wafer base. The second IC chip is edge-bonded to the first IC chip with oxide-to-oxide edge bonding. A chip-to-chip interconnect structure electrically couples the first IC chip and the second IC chip.

Abstract: A method of limiting the routing resources of an integrated circuit (IC) that are available for use when routing multi-fanout nets can include selecting a multi-fanout net comprising a source and a plurality of loads and identifying each region of the IC which does not include at least one of the plurality of loads. Each of the regions can have a defined geometry. A type of routing resource can be selected which has a physical orientation with respect to the IC that corresponds to the geometry of the regions of the IC. Each routing resource of the selected type that is located within a region of the IC which does not include at least one of the plurality of loads can be excluded from consideration when routing the multi-fanout net.

Abstract: A memory cell has a data value storage circuit and a data address circuit that includes a first address transistor formed in a first address transistor well and a second address transistor formed in a second address transistor well. The first address transistor is coupled between a data node and the second address transistor, and the second address transistor is coupled between the first address transistor and the data value storage circuit. The first address transistor well is coupled to an intermediate node between the first address transistor and the second address transistor, and the second address transistor well is coupled to a ground terminal.

Abstract: In one embodiment, a method and apparatus for shifting the bits of a data word are disclosed. For example, a deserializer according to one embodiment includes an input register bank for capturing serial data comprising n bits, an intermediate register bank, and a strobe mux coupled to an input of the intermediate register bank. An input of the intermediate register bank is coupled to an output of the input register bank. The strobe mux comprises a single multiplexer configured to select a bitslip strobe signal that controls an order in which the n bits of the serial data are captured in the intermediate register bank.

Abstract: A method of enabling the generation of reset signals in an integrated circuit is disclosed. The method comprises receiving information related to reset ports for a plurality of intellectual property cores in a design tool; providing an intellectual property core comprising a reset logic circuit adapted to generate a plurality of reset signals for the plurality of intellectual property cores; and generating, by the design tool, configuration data enabling programmable interconnects to couple a first reset signal of the plurality of reset signals to a first intellectual property core of the plurality of intellectual property cores and a second reset signal of the plurality of reset signals to a second intellectual property core of the plurality of intellectual property cores.

Abstract: A configurable memory manager is configurable with various configuration parameters. The configurable memory manager has client ports for receiving requests for accessing memories and memory ports for accessing respective memories. The client and memory ports are each independently configurable to specify the parameter of a data width of the port. The configurable memory manager includes a switch and a translator. The translator translates a virtual address in each of the requests into an identifier of one of the memories and a physical address in the memory. The switch transfers each request from the client port receiving the request to the memory port for accessing the memory identified by the identifier for the virtual address in the request.

Abstract: A computer-implemented method of automatic rate realization for implementing a circuit design within a programmable integrated circuit can include comparing data rates of clock domains of the circuit design with frequencies of available clock sources of the circuit design and determining which clock domains have data rates that match frequencies of clock sources. For each clock domain that has a data rate matching a frequency of a clock source, loads of the clock domain can be clocked using a multiple synchronous clock technique with the matching clock source. For each clock domain having a data rate that does not match a frequency of a clock source, loads of the clock domain can be clocked using a clock enable technique. The circuit design specifying the clock circuitry for each clock domain can be output.

Abstract: An embodiment of a method of forming a semiconductor device that includes a substrate having an active layer and interconnect formed on the active layer is described. The method includes: forming a dielectric layer above the interconnect having a tapered via exposing at least a portion of a first metal layer; forming an under-bump metallization (UBM) layer over the tapered via and the first metal layer to form a UBM bucket; and forming a dielectric cap layer over the dielectric layer and a portion of the UBM layer. The UBM bucket is configured to support a solder ball and can advantageously block all alpha particles emitted by the solder ball having a relevant angle of incidence from reaching the active semiconductor regions of the IC. Thus, soft errors, such as single event upsets in memory cells, are reduced or eliminated.

Abstract: A configurable arithmetic block for implementing arithmetic functions in a device having programmable logic is described. The configurable arithmetic block comprises a first plurality of registers coupled to receive input data; a second plurality of registers coupled to receive input data; an arithmetic function circuit having a plurality of arithmetic function elements, each arithmetic function element coupled to at least one other arithmetic function element of the plurality of arithmetic function elements and coupled to receive outputs of at least one of the first plurality of input registers and the second plurality of input registers; and an output coupled to the arithmetic function circuit. A method of implementing a configurable arithmetic block in a device having programmable logic is also disclosed.

Abstract: A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.

Abstract: A method of assigning a plurality of input/output (I/O) objects of a circuit design to banks of a programmable integrated circuit (IC) using integer linear programming can include storing a plurality of constraints that depend upon a plurality of variables, wherein the plurality of constraints regulate assignment of each of the plurality of I/O objects to banks of the programmable IC (125-184), and storing a linear function that depends upon the plurality of constraints and a plurality of cost metrics, wherein each cost metric imposes a penalty when a selected I/O object of the circuit design is assigned to a bank of the programmable IC that is different from a bank to which the selected I/O object is assigned within a reference solution that is infeasible (190).

Abstract: Access to data storage is described. A general-purpose processor and an auxiliary processing unit (APU) interface coupled to the general-purpose processor are provided. Data storage coupled to the general-purpose processor via the APU interface is provided for a fixed or low variable read latency access and a fixed write latency access to the data storage. A first instruction is passed to the general-purpose processor and to the APU interface. The first instruction is identified as part of a set of instructions accessible by the APU interface. The first instruction is used to write data into the data storage. A second instruction is passed to the general-purpose processor and to the APU interface. The second instruction is identified as part of the set of instructions accessible by the APU interface. The second instruction is used to read the data from the data storage, and the data is then output.

Abstract: A rank order filter and instantiation thereof in programmable logic is described. A maximum filter core frequency is determined for an input sampling frequency, a filter window height, and a number of input samples. The maximum filter core frequency is greater than the sampling frequency. The maximum filter core frequency may be insufficient for a word serial instantiation of the rank order filter in the programmable logic. The size of a fully parallel instantiation of the rank order filter may be excessive in programmable logic. Thus, a partially parallel filter core is instantiated for the rank order filter with overclocking.

Abstract: A processor local bus bridge for a processor block ASIC core for embedding in an IC is described. A core logic-to-core logic bridge includes a slave processor local bus interface, a crossbar switch coupled to the slave processor local bus interface and a master processor local bus interface coupled to the crossbar switch. The slave processor local bus interface and the master processor local bus interface are coupled to one another via the crossbar switch for bidirectional communication between a first and a second portion of core logic. The bridge provides rate adaptation for bridging for use of a frequency of operation associated with the crossbar switch which has substantially greater frequencies of operation than those associated with the core logic sides of the master and slave processor local bus interfaces.

Abstract: A method for adjusting a clock for a jitter sensitive circuit begins by determining a low noise phase region of a primary clock. The method then continues by adjusting phase of an auxiliary clock such that a transition of the auxiliary clock falls within the low noise phase region of the primary clock to produce an adjusted auxiliary clock.

Abstract: method of physical circuit design can include the steps of packing components of a circuit design that are dependent upon an architecture of the circuit design and assigning initial locations to each component of the circuit design. The components of the circuit design can be clustered by combining slices and including slices into configurable logic blocks according to design constraints, while leaving enough white space in the configurable logic blocks for post-placement circuit optimizations. The components of the circuit design then can be placed to minimize critical connections. The circuit design can be declustered to perform additional placer optimization tasks on the declustered circuit design.

Abstract: Methods for making and testing a semiconductor device with through substrate vias are described. In some examples, a method of making a semiconductor device includes: forming through substrate vias (TSVs) in a substrate having an integrated circuit (IC) die, the substrate including an active side and a backside, the active side having conductive interconnect formed thereon, the TSVs including exposed portions on the backside of the substrate; patterning first metal on the active side of the substrate to electrically couple the TSVs to a portion of the conductive interconnect; and coupling the exposed portions of the TSVs on the backside of the substrate to electrically couple together the plurality of TSVs.

Abstract: A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions, and is encoded to render the first portion operational and the second portion non-operational. At a boundary between the two portions, interconnect lines traversing the boundary include a first section in the first portion and a second section in the second portion. The second PLD die includes the first portion of the first PLD die, while omitting the second portion. The interconnect lines extending to the edge of the second die are coupled together in pairs. A software model for both die includes a termination model that omits the pair coupling, adds an RC load compensating for the omitted connection, and (for bidirectional interconnect lines) flags one interconnect line in each pair as being invalid for use by routing software.