Abstract: The logical functionality of a non-blocking multiplexer-based network is equivalent to a crossbar network with an ingress stage, a middle stage and an egress stage. Crossbar rows of the crossbar network include both outbound and inbound internal connections between other crossbar rows. The multiplexer-based network has corresponding rows and connections. The multiplexer-based network includes rows with an internal multiplexer for each respective outbound internal connection of a corresponding crossbar row. The internal multiplexer includes inputs for signals routable to the respective outbound internal connection. At least one global multiplexer provides a signal selected from a set of inputs that includes each input of the respective crossbar row.

Abstract: Interpolators for quadratic approximation for sinusoids are described. A sample source providing first order derivatives of sub-sampled sets of phase factor samples is used. A differentiator is coupled to receive the first order derivatives and configured to provide second order derivatives of the first order derivatives. A first scaling device is coupled to receive each of the first order derivatives. A second differentiator is coupled to receive each of the first order derivatives and configured to respectively provide second order derivatives of the first order derivatives. A second scaling device is coupled to receive the second order derivatives. A first integrator is coupled to receive output from the first scaling device for preloading, and to receive output from the second scaling device for integration. A third scaling device is coupled to receive output from the first integrator. A second integrator is coupled to receive output from the third scaling device.

Abstract: A multi-pass method of implementing a testbench can include, during a pre-processing pass, randomly selecting a configuration of the testbench and generating configuration data specifying the randomly selected configuration of the testbench. During a subsequent processing pass, the method can include compiling the testbench in accordance with the configuration data. Simulation can be performed using the testbench.

Abstract: A method (100) of estimating a performance characteristic of an integrated circuit (IC) design having an intellectual property (“IP”) core pre-characterizes an element type of the IC design to provide an estimation result of the element type (102-108). Mid-level elements of the IP are acquired (116). A user selects a value of a parameter of the IP core and the IC design is run on a design tool using the estimation result to model the mid-level elements of the IP core (118) to return a performance value of the IC design (120).

Abstract: Approaches for merging replicate logic blocks of a circuit design. Groups of replicate logic blocks in a placed circuit design are determined. For the replicate logic blocks in each group, a determination is made whether or not to merge replicate logic blocks in a subset of the replicate logic blocks into a respective single replacement logic block for the subset. In response to determining to merge the replicate logic blocks in the subset, the replicate logic blocks in the subset are replaced in the circuit design with the respective replacement logic block. The circuit design having the replacement logic block is stored in a memory by a processor executing the process.

Abstract: A programmable device with contact via programming to reduce leakage current and a method for reducing standby power for such programmable device are described. Configuration memory cells are identified responsive to instantiation of a user design in a test platform of the programmable device. The programmable device is via programmed during manufacturing thereof to not couple for programmability a first portion of the configuration memory cells and to form a first portion of the user design associated with the first portion of the configuration memory cells as hard-wired and to couple for programmability a second portion of the configuration memory cells for subsequent instantiation of a second portion of the user design in the programmable device.

Abstract: A bus-based logic block for an integrated circuit includes a provision for placing an arbitrary constant onto a data bus in the logic block. An exemplary logic block has multi-bit first and second inputs and a multi-bit output. The logic block includes a multi-bit multiplexer circuit, a multi-bit programmable logic circuit, and a constant generator circuit. The multiplexer circuit has a multi-bit first input coupled to a multi-bit first input of the logic block, a multi-bit second input, and a multi-bit output. The programmable logic circuit has a multi-bit first input coupled to the output of the multiplexer circuit, and a multi-bit output. The constant generator circuit has a multi-bit output coupled to the second input of the multiplexer circuit. Each bit of the logic block may be commonly controlled with all other bits of the logic block.

Abstract: A method and apparatus for a multiple lane transmission system that provides both a low latency mode of operation, while at the same time, provides reduced lane-lane skew. The overall transmission system operates as a mesochronous system, whereby each clock domain of the transmission system is synchronized to the leaf nodes of a global clock tree. A phase aligner is then used to align the phase of both the bit and byte clocks of each transmission lane to the clock signal generated at the leaf nodes of the global clock tree.

Abstract: Method and apparatus for implementing a circuit design for an integrated circuit is described. In one example, a first version of the circuit design is processed (408) with at least one design tool. Statistical data is captured (410) for the at least one design tool and operational attributes thereof are automatically adjusted (420) in response to the statistical data. A second version of the circuit design is processed (422) with the at least one design tool having the adjusted operational attributes. In another example, the circuit design is processed (506) with at least one design tool in a first iteration. Statistical data is captured (508) for the at least one design tool and operational attributes thereof are automatically adjusted (514) for a second iteration in response to the statistical data of the first iteration. The circuit design is re-processed (516) with the at least one design tool having the adjusted operational attributes in the second iteration.

Abstract: Circuit placement for increasing circuit packing density for an integrated circuit is described. A design is synthesized and mapped. Components of the design are placed to provide a first placed design. A congestion density map is generated for the first placed design. A congestion region in the congestion density map is identified and targeted for determining if the first placed design has a control set conflict. A first circuit object associated with the control set conflict is selected and either re-placed or re-synthesized to at least diminish the control set conflict.

Abstract: A method of estimating resource requirements for a circuit design is disclosed. The method comprises identifying intermediate circuit modules of a netlist associated with the circuit design; accessing a library of resource requirements for intermediate circuit modules of netlists for circuit designs; selecting intermediate circuit modules of the library according to predetermined parameters for the circuit design; and generating an estimate of resource requirements for the circuit design based upon resource requirements of the selected intermediate circuit modules.

Abstract: Methods of providing error correction in configuration bitstreams for programmable logic devices (PLDs). While any error correction method can be used, in one embodiment a Hamming code is applied to instructions in the configuration bitstream, while a product code is applied to configuration data. Thus, the higher overhead required for a Hamming code applies to only a few words in the bitstream. The instructions are corrected on receipt of the word that includes the Hamming code, so the instructions are executed correctly even if a transmission error has occurred. However, configuration data can be stored in the configuration memory without correction. With a product code, the exact location of an erroneous bit is not known until the end of the transmission, when a parity word is received. At this time, the PLD can go back and correct erroneous bits in the configuration data prior to enabling the newly loaded design.

Abstract: A computer-implemented method of predicting timing characteristics within a semiconductor device can include determining configuration information for the semiconductor device and determining a measure of timing degradation for data signals of the semiconductor device according to the configuration information. The measure of timing degradation for the data signals can be output.

Abstract: A method of configuring a device having programmable logic is disclosed. The method comprises generating a netlist associated with a circuit design; coupling the netlist to the device having programmable logic; performing a re-targeting function using a circuit on the device having programmable logic; generating configuration bits for configuring the programmable logic; and configuring the programmable logic to implement the circuit design according to the configuration bits based upon the netlist and results of the re-targeting function.

Abstract: Approaches for validating a design for a packet processing circuit. A method inputs a high-level language specification of a first format of an input packet. From the input specification, a plurality of high-level input packets having the first format are generated, with each field of each input packet having a value consistent with the packet specification. The packet processing circuit is simulated using a first model with input of the high-level input packets, and a first plurality of high-level output packets are output. The high-level input packets are translated into low-level input packets. The packet processing circuit is simulated using a second model with input of the low-level input packets, and a plurality of low-level output packets are output and translated into a second plurality of high-level output packets. The first and second pluralities of high-level output packets are compared to corresponding expected output packets, and comparison results stored.

Abstract: A semiconductor device includes a field-programmable gate array (“FPGA”) die (202) having a frame address bus (604), a frame data bus (608), and a second integrated circuit (“IC”) die (204) attached to the FPGA die. An inter-chip frame address bus (605) couples at least low order frame address bits of a frame address of a frame between the FPGA die and the second IC die. The inter-chip frame address bus includes a first plurality of contacts (614) formed between the FPGA die and the second IC die. An inter-chip frame data bus couples frame data of the frame between the FPGA die and the second IC die. The inter-chip frame data bus includes a second plurality of contacts (616) formed between the FPGA die and the second IC die.

Abstract: A method of operating an integrated circuit having a circuit block configurable by a configuration memory is disclosed. The method includes determining whether to operate the circuit block in a normal operation mode or a low power mode. The configuration memory is loaded with normal operation mode configuration data for the circuit block if the normal operation mode is determined. If the low power mode is determined, the configuration memory is loaded with low power mode configuration data for the circuit block.

Abstract: A method of bridging a plurality of buses within a bus bridge can include determining whether a queue of the bus bridge includes a transaction request directed to a restricted address range and, for each received transaction request, determining whether an address to which the transaction request is directed is within the restricted address range. Each transaction request received by the bus bridge can be selectively rejected according to whether the address to which the transaction request is directed is within the restricted address range and whether the queue includes a transaction request directed to the restricted address range.

Abstract: Method and apparatus for integrating capacitors in stacked integrated circuits are described. One aspect of the invention relates to a semiconductor assembly having a carrier substrate, a plurality of integrated circuit dice, and at least one metal-insulator-metal (MIM) capacitor. The integrated circuit dice are vertically stacked on the carrier substrate. Each MIM capacitor is disposed between a first integrated circuit die and a second integrated circuit die of the plurality of integrated circuit dice. The at least one MIM capacitor is fabricated on at least one of a face of the first integrated circuit die and a backside of the second integrated circuit die.

Abstract: A self-synchronizing system that provides a master system component and a master clock source to provide a stable timing reference to the master system component. Timing information is then propagated throughout the system via encoded transmissions containing the timing information, or conversely, propagated by request via a training sequence. All system components other than the master system component do not require a separate clock input, since frequency coherency is maintained by internal time bases that have been calibrated to the frequency of the propagated timing information.