Abstract: A circuit has first portion that receives data at a first rate; a second portion that outputs data at a second rate synchronized to and different from the first rate; a third portion that transfers data from the first portion to the second portion; and a fourth portion that generates an error detected signal in response to a disruption in the synchronism between the first and second rates. A different aspect involves a method that includes: receiving data at a first rate in a first portion; transferring data from the first portion to a second portion; outputting data at a second rate from the second portion, the second rate being synchronized to and different from the first rate; and generating an error detected signal in response to detection of a disruption in the synchronism between the first and second rates.

Abstract: A hardware interface in an integrated circuit is disclosed. The hardware interface comprises data storage coupled to store and provide data; a data shifter coupled to the data storage to at least bit shift the data obtained from the data storage; and a control circuit coupled to the data storage and the data shifter for controlling a transfer of the data from the data storage and the data shifter. The control circuit comprises a state machine for controlling operation of the data storage and the data shifter; and the state machine is programmable responsive to code executable by a processor coupled to an auxiliary processing unit to adapt to the auxiliary processing unit.

Abstract: A method and system are disclosed. The system includes a trusted loader. The method includes downloading an IP core from a vendor to a target device. The IP core is received in an encrypted form at the target device, which can be, for example, a programmable logic device.

Abstract: An embodiment of a method to form a hybrid integrated circuit device is described. This embodiment of the method comprises: forming a first die using a first lithography, where the first die is on a substrate; and forming a second die using a second lithography, where the second die is on the first die. The first lithography used to form the first die is a larger lithography than the second lithography used to form the second die. The first die is an IO die.

Abstract: Data recovery, as well as associated circuitry and system, is described. An input word stream having a word width of at least one word is obtained and a sliding window is applied to it to resolve phases. Scores for phases are determined at least in part by: subdividing the sliding window into sample portions; applying a homogeneity function to each of the sample portions to determine respective values therefor; and summing sets of the values respectively associated with the phases to provide the scores. A score is selected from the scores according to at least one criterion to select a phase from the phases. A portion of a delayed version of the input word stream is sampled by application of the sliding window thereto using the phase selected to output sampled bits.

Abstract: A method of detecting an error when loading a programmable integrated circuit (IC) can include detecting a predetermined bit pattern indicating a start of a bitstream within the programmable IC, starting a timer within the programmable IC responsive to detecting the predetermined bit pattern, and determining whether a bitstream load complete condition has occurred prior to expiration of the timer. When the timer expires prior to an occurrence of the bitstream load complete condition, at least one recovery action can be implemented.

Abstract: Method and apparatus for block boundary detection is described. A signal is received. The signal is quantized to provide a quantized signal to at least one correlator, the quantized signal being a sequence of samples. The sequence of samples and a reference template including totaling partial results from the at least one correlator are cross-correlated to provide a result, the result being a symbol timing synchronization responsive to the cross-correlation also known as block boundary detection. The cross-correlation is provided in part by combining by exclusive-ORing a regression vector obtained from the sequence of samples and a coefficient term vector obtained from the reference template.

Abstract: A columnar programmable device (PD) design converted to a columnar application specific integrated circuit-like (ASIC-like) design is described. A user design is instantiated in a PD having a columnar architecture associated with the columnar PD design. The columnar architecture has adjacent columns of circuitry, and one or more of the columns of circuitry as associated with instantiation of the user design in the PD are identified. At least a portion of one or more of the identified columns are swapped with application specific circuitry for implementing all or part of the user design for converting the columnar PD design to the columnar ASIC-like design.

Abstract: An embodiment of a method of enhancing security of internal memory is disclosed. For this embodiment of the method, the application specific block is operated in a functional mode, and a reset of the application specific block is initiated. From a built-in self-test engine, at least one write to the internal memory is initiated in response to the reset initiated, where the at least one write overwrites data stored in the internal memory during a reset mode.

Abstract: A method of verifying a triple module redundant circuit. The method comprises providing three circuits, each comprising a redundant circuit; coupling a feedback voter circuit at the output of each circuit of the three circuits, each feedback voter receiving the output of each of the three circuits; disabling a first circuit of the three circuits; enabling the first circuit; disabling a second circuit of the three circuits; and verifying the output of the triple module redundant design to determine whether an error has occurred. A article of manufacture for verifying a design implemented as a triple redundancy module is also described.

Abstract: A capacitor in an integrated circuit (“IC”) has a first node conductor formed in a first metal layer of the IC with a first spine extending along a first direction, a first vertical element extending from the first spine along a second direction perpendicular to the first direction. A first capital element extends along the first direction, and a first serif element extends from the capital element. The capacitor also has a second node conductor having a second spine, a second vertical element extending from the second spine toward the first spine, a second capital element, and a second serif element extending from the second capital between the first vertical element and the first serif element.

Abstract: A method of input/output (I/O) block placement assigned to an input/output bank includes formulating a placement algorithm using integer linear programming (ILP) and simultaneously placing single groups and Relatively Placed Module (RPM) groups of I/O blocks in the I/O bank. The method further includes determining a placeability matrix P and a binary assignment matrix X used for the ILP. The method can further eliminate all assignment matrix elements of X equal to 0 in the integer linear programming and re-index any remaining elements. The method can further place all I/O blocks according to a solution if solving of the standard ILP formulation results in a feasible solution. Optionally, the method generates a placement solution that is as close as possible to an external reference solution specified by designer. Optionally, the method analyzes which constraints were violated and generates useful error information.

Abstract: A circuit for protecting a transistor during the manufacture of an integrated circuit device is disclosed. The circuit comprises a transistor having a gate formed over an active region formed in a die of the integrated circuit device; a protection element formed in the die of the integrated circuit device; and a programmable interconnect coupled between the gate of the transistor and the protection element, the programmable interconnect enabling the protection element to be decoupled from the transistor.

Abstract: An integrated circuit having a plurality of data transceivers positioned on opposite ends of the integrated circuit is disclosed. The integrated circuit comprises a first plurality of data transceivers positioned in a column on a first end of the integrated circuit and a second plurality of data transceivers positioned in a column on a second end. A circuit is preferably positioned between the first plurality of data transceivers and the second plurality of data transceivers. The circuit could comprise, for example, circuits for implementing a programmable logic device. The circuitry of the plurality of data transceivers is also preferably arranged such that analog circuitry is positioned closer to an end of the integrated circuit than the digital circuits to reduce interference with the analog circuits. According to another aspect of the invention, the data transceivers are formed on layers to reduce the amount of interference.

Abstract: A double exposure semiconductor process is provided for improved process margin at reduced feature sizes. During a first processing sequence, features defining non-critical dimensions of a polysilicon interconnect structure are formed, while other portions of the polysilicon layer are left un-processed. During a second processing sequence, features that define the critical dimensions of the polysilicon interconnect structure are formed without the need to execute a photoresist trimming procedure. Accordingly, only an etch process is executed, which provides higher resolution processing to create the critical dimensions needed during the second processing sequence.

Abstract: An integrated circuit (IC) has an under-bump metal (UBM) pad disposed between a solder bump and a semiconductor portion of the IC. The UBM pad has a contact perimeter formed with the solder bump. The UBM pad extends beyond the contact perimeter a sufficient distance to block alpha particles emitted from the surface of the solder bump from causing an upset event in the semiconductor portion.

Abstract: A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication.

Abstract: An embodiment of the present invention provides for the ad-hoc configuration of femtocells using spectrum sensing for the selection of spectrum channels. One or more embodiments of the invention determine frequency bands that are not reserved by macrocells in a location, and perform spectrum sensing to determine communication channels in unreserved frequency bands that are being used by other femtocells in range. In this manner, femtocells can be deployed and configured in an ad-hoc manner without external coordination or control between deployed femtocells.

Abstract: Induced crosstalk is predicted for the input/output pins of a programmable logic device. Signal edge rates for the input/output pin are determined from selected interface protocols for the input/output pins. For each pair of the input/output pins, a first coupling coefficient specifies a coupling between the pair of input/output pins within a package for mounting the programmable logic device to a printed circuit board. A depth is input for each via coupled to an input/output pin by the printed circuit board. From the via depths, a second coupling coefficient is determined for each pair of the input/output pins that satisfy a separation criterion. For each of the input/output pins, a predicted value of an induced crosstalk is determined from the first and second coupling coefficients for each pair that includes the input/output pin and another input/output pin, and from the signal edge rate of this other input/output pin.

Abstract: A method and apparatus for aligning the phases of digital clock signals are disclosed. For example, a phase alignment circuit according to one embodiment includes a frequency adjuster comprising a first plurality of inputs, where at least some of the first plurality of inputs are coupled to an output of a digital clock of an integrated circuit, a phase adjuster comprising a second plurality of inputs, where at least some of the second plurality of inputs are coupled to a plurality of outputs of the frequency adjuster, and an XOR gate comprising a third plurality of inputs, each of the third plurality of inputs being coupled to one of the plurality of outputs of the frequency adjuster.