Abstract: A programmable logic device can include a logic core in low power mode, a source input/output (I/O) bank including at least one source I/O pin, wherein the source I/O bank operates in normal operating mode, and a destination I/O bank including at least one destination I/O pin, wherein the destination I/O bank operates in normal operating mode. The programmable logic device also can include a bypass routing bus coupled to the source I/O bank and the destination I/O bank, wherein the bypass routing bus detects an I/O signal from the source I/O pin, responsively generates a bypass signal that is provided to the destination I/O bank and, responsive to the bypass signal, generates an output bypass signal on the destination I/O pin.

Abstract: Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs of the groups are related by an association of at least one routing resource in one group of a pair of groups capable of being electrically connected to at least one other routing resource in another group of the pair of groups.

Abstract: An integrated circuit includes an electronic fuse (“E-fuse”) cell having a fuse link and an E-fuse programming current generator. The fuse link has a width (FLw) and a thickness (FLT) and is fabricated from a layer of link material. An E-fuse programming current generator includes a reference link array having a plurality of reference links. Each of the reference links has the fuse link width and the fuse link thickness, and is fabricated from the layer of link material.

Abstract: A method and apparatus for a receive equalizer of a gigabit transceiver that is reconfigurable to support multiple communication standards. Communication standards having variable common mode and coupling requirements are accommodated through the use of reconfigurable integrated circuits (ICs), such as field programmable gate arrays (FPGAs), that provide a plurality of reconfigurable transceivers that are programmable through configuration, or partial reconfiguration, events. The reconfigurable transceivers apply internally generated common mode voltage signals to the differential input in support of the various communication standards.

Abstract: Method and apparatus for modeling multiple instances of an electronic circuit using an imperative programming language description is described. In one example, a program is defined using an imperative programming language. The program includes multiple calls to a function. The function includes a persistent variable associated with an internal state of the electronic circuit. The function is configured to initialize the persistent variable based on at least one call path to the function in the program.

Abstract: An integrated circuit has a differential I/O buffer (102) capable of being operated in a single-ended mode. The I/O buffer includes circuitry (114 or 112) for reducing leakage current between the differential I/O pins (P, N) when an undershoot event occurs on a pin when operated single-ended mode. In one case, a differential termination circuit (114, 200) includes a differential termination isolation circuit (202) that isolates the termination load (201) and termination load switch (208) from the single-ended pin. Alternatively or additionally, a differential output driver (300) of the I/O buffer switches a common bias voltage (ncom) to a supply voltage (VCOO) in single-ended mode to insure the transistors (A2, B1) in the driver legs remain OFF during an undershoot event.

Abstract: An ASIC block embedded in a host IC has a first clock domain with a first frequency of operation that is at least equal to a second frequency of operation of a second clock domain in the host IC but external to the ASIC block. FPGA logic in the second clock domain interfaces with the ASIC block; and a PLL located in the host integrated circuit but external to the ASIC block is coupled to receive a reference clock signal and configured to generate clock signals. Two of the clock signals are respectively sent to the FPGA logic and the ASIC block to make one appear to be produced earlier in time than the other with respect to the ASIC block to compensate for a clock insertion delay and for a clock-to-output time associated with the FPGA logic that at least approximates zero.

Abstract: Framing transmit encoded output data begins by determining a scrambling remainder between scrambling of an input code word in accordance with a 1st scrambling protocol and the scrambling of the input code word in accordance with an adjustable scrambling protocol. The processing continues by adjusting the adjustable scrambling protocol based on the scrambling remainder to produce an adjusted scrambling protocol. The processing then continues by scrambling the input code word in accordance with the 1st scrambling protocol to produce a 1st scrambled code word. The processing continues by scrambling the input code word in accordance with the adjusted scrambling protocol to produce a scrambled partial code word. The processing continues by determining a portion of the 1st scrambled code word based on the scrambling remainder. The process then continues by combining the scrambled partial code word with the portion of the 1st scrambled code word to produce the transmit encoded output data.

Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

Abstract: In one embodiment, an integrated device is disclosed. For example, in one embodiment of the present invention, a device comprises a core module for providing one or more output signals. The device comprises an output logic module for receiving the one or more output signals and an input logic module, wherein the one or more output signals are received by the input logic module via one or more feedback paths, where the one or more output signals are forwarded back to the core module.

Abstract: A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed circuit, wherein the programmed circuit includes an input sequential element and an output sequential element. The method continues by providing a test input to the programmed circuit. The method continues by triggering the input sequential element to temporarily store the test input based on a first edge of the test clock. The method continues by triggering the output sequential element to temporarily store a test output of the programmed circuit based on a second edge of the test clock. The method continues by capturing the test output of the programmed circuit in accordance with the second edge of the test clock.

Abstract: A computer-implemented method of improving timing of a circuit design for a programmable logic device can include identifying a timing critical wire of the circuit design and determining a fanout free cone coupled to a plurality of leaf nodes, wherein the critical wire links a critical leaf node of the plurality of leaf nodes with the fanout free cone. At least one leaf node set can be selected, wherein the leaf node set includes a plurality of symmetric leaf nodes including the critical leaf node and at least one non-critical leaf node. At least two leaf nodes of a leaf node set can be swapped in the circuit design. The circuit design can be output.

Abstract: A dual clock interface for an integrated circuit is described. An integrated circuit includes interface circuitry. The interface circuitry has a hardwired logic block. The hardwired logic block has a clock divider circuit coupled to receive a user clock signal and a core clock signal for dividing the core clock signal responsive to a frequency of the user clock signal to provide a divided clock signal with edges aligned to the core clock signal. The divided clock signal has the frequency of the user clock signal and a phase relationship of the user clock signal. User-side logic is coupled to receive the divided clock signal for the controlled passing of information responsive to the divided clock signal. Core-side logic is coupled to receive the core clock signal for the controlled passing of information responsive to the core clock signal.

Abstract: Performance monitors (PMs) are provided in a system to identify the execution time for data being transferred within the system and determine operation parameters of the system based on the rate data is transferred. The operation parameters are then used to configure hardware within the system. The PMs can provide a histogram of the transactions usable to evaluate system performance. The PMs can provide a time line diagram of the transactions to show the specific order the transactions occurred. The PMs can be provided in a multi-port memory controller (MPMC) to monitor the speed of read and write transactions from the MPMC ports, and used to configure logic within the MPMC to maximize the rate of data flow.

Abstract: A method of creating a secure intellectual property (IP) representation of a circuit design for use with a software-based simulator can include translating a hardware description language representation of the circuit design into an encrypted intermediate form and compiling the intermediate form of the circuit design to produce encrypted object code. The method further can include linking the encrypted object code with a simulation kernel library thereby creating the secure IP representation of the circuit design. The secure IP can include an encrypted simulation model of the circuit design and a simulation kernel configured to execute the encrypted simulation model.

Abstract: An external storage device may transmit encrypted configuration data to a PLD during a configuration operation without transmitting the encryption key to the PLD and without retaining decryption information in the PLD. During a set-up operation, the encryption key is provided to the PLD, which generates an ID code upon power-up. The PLD generates a correction word in response to the encryption key and the ID code. The correction word is output from the PLD, which is powered-down, and is stored with the encrypted configuration data in the storage device. Then, during a configuration operation, the PLD is powered-on and re-generates the ID code. The correction word and the encrypted configuration data are transmitted to the PLD, which generates a decryption key in response to the re-generated ID code and the correction word.

Abstract: A programmable device having a processing core is configured to use a subset of configuration memory cells as read/write memory. The subset of memory cells is a don't care set that includes configuration memory cells that can be set or reset without modifying the function or behavior of the configured circuits of the programmable device.

Abstract: A state machine is provided with outputs that have programmable delays that enable the state machine to be compatible with a number of different devices. The state machine uses shift register look up tables (SRLs) to provide variable output delays. The state machine can be provided in the BRAM of an FPGA, and can be used to provide control logic in a multi-port memory controller (MPMC). The MPMC with such a state machine can then connect to multiple different types of memory devices either simultaneously or separately.

Abstract: An electronic fuse memory array has an array core with a plurality of selectable unit cells. A unit cell has a fuse and a cell transistor (M12). A programming current path goes through the fuse and the cell transistor to a word line ground and a read current path also goes through the fuse and the cell transistor to the word line ground.

Abstract: A method of sampling a frequency difference in an integrated circuit is disclosed. The method comprises the steps of receiving a clock signal in a first clock domain; comparing a count of the clock signal in the first clock domain to a predetermined value N; converting the result of the comparison to a second clock domain; and generating an error signal representing the difference between the count of the first clock signal and the count of a second clock signal in the second clock domain. A circuit for sampling a frequency difference in an integrated circuit is also disclosed.