Abstract: Method and apparatus for compensating an integrated circuit design for mechanical stress effects. One aspect of the invention relates to designing an integrated circuit. Layout data is obtained that describes layers of the integrated circuit. At least one of the layers is analyzed to detect at least one structure susceptible to damage from mechanical stress. A bias is automatically added to each of the at least one structure to reduce mechanical stress of the at least one structure as fabricated. Augmented layout data is then provided for the integrated circuit.

Abstract: Recesses are formed in the drain and source regions of an MOS transistor. The recesses are formed using two anisotropic etch processes and first and second sidewall spacers. The recesses are made up of first and second recesses, and the depths of the first and second recesses are independently controllable. The recesses are filled with a stressed material to induce strain in the channel, thereby improving carrier mobility. The widths and depths of the first and second recesses are selectable to optimize strain in the channel region.

Abstract: A method is provided that speeds up software testing using abbreviation of software tests that skips the execution of a portion of the software test. Intermediate results are generated for one or more software tests, with each intermediate result corresponding to a software test, and a respective key is generated from each intermediate result. A determination is made whether the respective key for each intermediate result is stored in a file cache used for storing files under keys. Generation of a final result for the corresponding software test of each intermediate result is bypassed in response to the respective key being present in the file cache. A final result for the corresponding software test of each intermediate result is generated from the intermediate result in response to the respective key not being present in the file cache. The respective key is stored in the file cache in response to generation of each final result.

Abstract: A method for generating a hardware description language (HDL) specification of a processor of network packets. Independent sets of interdependent handlers are determined from a specification of the handlers for processing the network packets. Either a first pipeline or a cluster of threads is selected for a corresponding architecture for each independent set. The corresponding architecture has one or more concurrent units for each interdependent handler in the independent set. Each concurrent unit is either a stage of the first pipeline or a thread of the cluster. Each action of each interdependent handler in each independent set is assigned to a concurrent unit for the interdependent handler. Each of these actions is also assigned to a stage of a second pipeline for the concurrent unit. The HDL specification of the processor is generated specifying the corresponding architecture for each independent set and the second pipeline for each concurrent unit.

Abstract: A memory coupled to a programmable logic device (PLD) is configured through the PLD's JTAG port. A soft core loaded into the PLD connects to the JTAG port and memory. An external programming host device connects to the JTAG port, sends instructions and data to and receives data from the memory via the JTAG port and soft core. A synchronization JTAG instruction is loaded, and a Shift Data state of the JTAG port state machine is used. The programming host device and soft core are synchronized, and a memory chip select is asserted. A memory instruction, such as READ, WRITE or ERASE is loaded into the memory. An RTI state of the state machine is used to wait for instruction completion and the chip select is deasserted. Another instruction is processed starting with using the Shift Data state. Alternatively, a PLD Shift Data Register is used in conjunction with the soft core.

Abstract: Circuits and methods of suppressing signal glitches in an integrated circuit (IC). A glitch on a signal entering a clock buffer, for example, is prevented from propagating through the clock buffer. In some embodiments, a latch is added to an input clock path that detects a transition on the input signal, and then ignores any subsequent transitions for a time delta that is determined by a delay circuit. In some embodiments, a multiplexer circuit is used to select between the input clock signal and the output clock signal, with changes on the input clock signal not being passed through the multiplexer circuit unless the time delta has already elapsed. In some embodiments, the delay is programmable, pin-selectable, or self-adapting.

Abstract: A semiconductor package having a substrate and a die includes a plurality of conductive posts attached to the substrate and bonded to an active surface of the die via a plurality of corresponding microbumps. The conductive posts are flexible and extend beyond the top surface of the substrate a sufficient distance to absorb lateral forces exerted upon the microbumps.

Abstract: A buffer management system for a data processing system can include a plurality of tokens wherein each token is associated with one of a plurality of buffers, and a plurality of first-in-first-out (FIFO) memories. Each FIFO memory can be associated with a stage of the data processing system and is configured to store at least one of the tokens. The buffer management system also can include control logic configured to determine a state of one or more selected buffers and transfer the token associated with the selected buffer from a source FIFO memory to a target FIFO memory. The target FIFO memory can be selected according to the state of the selected buffer.

Abstract: Implementing a type-safe heterogeneous containers in a memory arrangement of a computing system. In one embodiment, a main object of a class is specified in program source code. The class has a variant type, and the variant type provides at least two different data types, at least one of which is a linear array of objects of one of the data types. The class includes methods for putting and getting a variant object of the variant type in and from the main object. An application of a visitor method, which includes a respective operator for each of the different data types, is specified in the program source code for each method for getting a variant object from the main object. Compilation of the source code results in code that executes the one of the operators corresponding to the data type of a referenced variant object of the main object.

Abstract: A method and apparatus for advantageously utilizing the reset state of an RTZ shift register to guarantee proper data alignment at the feedback taps to facilitate decision feedback equalization (DFE). An input data stream (DATA) is sliced into an even data stream and an odd data stream. Each bit of the even data stream is propagated through RTZ latches and each bit of the odd data stream is propagated through RTZ latches. At any given instant in time, half of the RTZ latch outputs contain zero information, so that each latch output may be summed in a current mode without the need for any intervening logic. The input data stream is then summed in current mode with the feedback data and converted to voltage prior to sampling of the currently received data bit.

Abstract: Method and apparatus for dynamically connecting modules within a programmable device is described. In an example, a programmable device is programmed with modular circuits. A bitstream is obtained from a database. The bitstream includes a first portion associated with a module and a second portion associated with an interface to the module. The bitstream is then modified with configuration data to connect the interface to one or more of the modular circuits. The programmable device is then configured using the modified bitstream.

Abstract: Method and apparatus for communication between hardware blocks and a processor in a programmable logic device is described. A shared memory is provided along with a memory controller for controlling access to the shared memory. An interface is configured to receive auxiliary instructions from the processor, select the hardware blocks for the requested tasks in response to the auxiliary instructions, notify the hardware blocks of those tasks, and arbitrate access to the memory controller among the hardware blocks.

Abstract: Implementing an electronic design having software-implemented blocks and hardware-implemented blocks. A specification of the electronic design is created in response to selection of blocks from a library, and at least one of the blocks is available for implementation in a selectable one of a software implementation for an embedded processor on a programmable logic device (PLD) and a hardware implementation on the PLD. A specification of each block in a first subset is obtained from the library and translated into an execution function of the software implementation of the block. Peripheral functions are generated for connections between blocks in the first subset and blocks in a second subset, which are designated for a hardware implementation on the PLD. A program is generated that invokes each peripheral function and each execution function in an order determined from the interconnections between the blocks.

Abstract: A method of buffering data in a circuit processing data in both a natural address order and a modified address order is described. The method comprises the steps of storing a first block of data according to a first addressing order of a natural address order or a modified address order; reading the first block of data stored in a buffer according to the other addressing order of the natural address order and the modified address order; and simultaneously writing a second block of data to the buffer in the other addressing order while reading the first block of data stored in a buffer according to the other addressing order.

Abstract: A voltage regulator and method of voltage regulation for a power-on reset condition are described. Voltage regulation control signals responsive to the power-on reset condition are obtained. The control signals are generated with a first voltage to be associated with a second voltage to provide a first power-on-reset signal and a second power-on-reset signal which are opposite in state to one another. A portion of driver logic is tri-stated responsive to the control signals, and the second power-on-reset signal to at least impede supply to supply current leakage. Voltage is pulled up on a first output port and a second output port of the driver logic responsive to the first power-on-reset signal. A portion of a semiconductor substrate is electrically coupled to a higher one of a first voltage and a second voltage responsive to the pulling up to at least further impede the supply to supply current leakage.

Abstract: A method of partially reconfiguring a field programmable gate array (FPGA) with at least one design that has interdesign routing with at least one other design programmed into the FPGA. A first configuration data set implements a first design in a first area of the FPGA, a second design in a second, non-overlapping area, and at least one bus macro that defines a bus interface between the first design and the second design. The bus interface includes a set of signal lines coupled to the first and second designs and logic that controls input and output of signals over the signal lines. A second configuration data set implements a modified version of the first design in the first area and does not implement any version of the second design. The FPGA is configured with the first configuration data set, and then partially configured with the second configuration data set.

Abstract: A system detects symbols communicated from multiple transmitting antennas to multiple receiving antennas. A first detector determines the symbols from respective partial distances of potential choices for symbols from a constellation. A second detector determines the symbols from respective partial distances of more potential choices. The first and second detectors determine their partial distances from signals received at the receiving antennas. The second detector has a lower bit error rate than the first detector. The potential choices for the second antenna are smaller than the potential choices for the first antenna in response to a signal-to-noise ratio (SNR) being higher than a threshold. An evaluator estimates the SNR of the signals received at the receiving antennas. The evaluator enables the first detector in response to the SNR being lower than the threshold, and the evaluator enables the second detector in response to the SNR being higher than the threshold.

Abstract: Various approaches for incrementally updating the timing of an implementation of an electronic circuit design are disclosed. In one approach, a subset timing graph is selected from a primary timing graph. Alternative subset timing graphs are generated that are functionally equivalent and structurally different with respect to the selected subset timing graph. For each of the alternative timing graphs, a respective timing metric is determined. The determined timing metrics and a timing metric for the selected subset timing graph are compared. An alternative timing graph is selected in response to the comparison. Structurally different portions of the selected one of the one or more alternative timing graphs are verified with regard to the design constraints. The structurally different portions are stored to the primary timing graph.

Abstract: In one embodiment, an integrated device is disclosed. For example, in one embodiment of the present invention, a device comprises a logic control, and a combination differential driver coupled to the logic control, wherein the logic control receives a control signal for configuring the combination differential driver as a Low Voltage Differential Signaling (LVDS) driver or as a Transition Minimized Differential Signaling (TMDS) driver.

Abstract: Various approaches for detection of an unwanted function implemented in an integrated circuit (IC) are described. A controller is implemented on the IC, and at a first time while the IC is operating according to a circuit design, the controller reads a first data set from a subset of memory cells. The subset of memory cells stores state information of the circuit design. The controller determines whether the first data set is different from a second data set. In response to the first data set being different from the second data set, the controller outputs a threat signal that indicates the presence of unauthorized logic in the circuit design.