Abstract: A multi-mode circuit for a self-timed integrated circuit is provided. The multi-mode circuit is programmable to operate in two or more modes, and is coupled to require, in each mode, receipt of a token on at least one of first, second, or third inputs before providing an output token. The multi-mode circuit is further coupled to require tokens on different inputs in at least two different modes. The multi-mode circuit can be an output circuit for a logic block in an integrated circuit including an array of interconnected logic blocks, where each logic block includes a logic circuit and a multi-mode circuit. One input of each multi-mode circuit can be programmably coupled to a select output of a multi-mode circuit in an adjacent logic block. Based on the programmed mode and the tokens received, the circuit routes data between inputs and outputs of the circuit.

Abstract: A circuit structure implements a logical AND gate that operates correctly when provided with inputs at two different power-high voltages. The circuit structure includes a pulsed driver circuit operating at a first power high voltage, and an AND logic circuit operating at a second power high voltage higher than the first power high voltage. The pulsed driver circuit has an input operating at the first power high voltage and provides an output operating at the first power high voltage. The first input of the AND logic circuit operates at the second power high voltage, the second input of the AND logic circuit is coupled to the output of the pulsed driver circuit and operates at the first power high voltage, and the output of the AND logic circuit operates at the second power high voltage. An exemplary implementation of the AND logic circuit is described.

Abstract: A method of implementing a circuit in a device having programmable logic is disclosed. The method comprises implementing a circuit in the programmable logic of the device; storing data in a block of random access memory; performing a partial reconfiguration of the device, where new data is stored in the block of random access memory; and accessing the new data. A system of implementing a circuit in a device having programmable logic is also disclosed.

Abstract: Circuits for merging data streams in a self-timed programmable integrated circuit. A programmable integrated circuit includes interconnected logic blocks, each including a logic circuit and an output multiplexer circuit including an arbiter and a multiplexer. Each arbiter is coupled to receive ready signals provided with first and second outputs of the logic circuit. Each multiplexer has first and second data inputs coupled to the outputs of the logic circuit, a select input programmably coupled, in one of a plurality of operating modes, to an arbiter output, and a data output coupled to an output of the logic block. The output multiplexer circuit provides an output token only when a first token indicates valid new data on the arbiter output and a second token indicates valid new data on one of the data inputs, and stores a third token received on the other data input until the other data input is selected by the multiplexer.

Abstract: Circuits enabling feedback paths in a self-timed integrated circuit. Each of a plurality of interconnected logic blocks includes a logic circuit having first and second outputs, and means for placing, during an initial cycle, a self-timed first data signal on the second output onto a logic block output, and for placing, during subsequent cycles, a self-timed second data signal on a selected one of the first or second outputs onto the logic block output. Initially, an output token is provided only when valid new data is received on the second output and on a select signal. Subsequently, the output token is provided only when either the first output of the logic circuit is selected, and valid new data is received on the first output and on the select signal; or the second output of the logic circuit is selected, and valid new data is received on the first and second outputs and on the select signal.

Abstract: A method of adapting parameters for a predistortion circuit in an integrated circuit is disclosed. The method comprises receiving, at the predistortion circuit, an input signal to be amplified by a power amplifier; determining a value associated with an information tag for the input signal; applying parameters to the predistortion circuit based upon the determined value; receiving an output of the power amplifier at an input of the integrated circuit; comparing an output of the predistortion circuit with the output of the power amplifier; and generating updated parameters to be applied to the predistortion circuit. An integrated circuit having a circuit for adapting parameters for a predistortion circuit of the integrated circuit is also disclosed.

Abstract: Reduced mounting inductance and/or an increased self-resonant frequency range of operation for capacitor circuits of a circuit board is described. The circuit board has a mounting pad for coupling a capacitor to at least three vias arranged in a pattern and coupled to the mounting pad at least three discrete locations to reduce mounting pad inductance. Alternatively or additionally, top and bottom mounted capacitors to the circuit board have a physically and electrically common through via to provide a self-resonant frequency range of operation.

Abstract: A cascading output structure for logic blocks in an integrated circuit. An exemplary integrated circuit includes an array of interconnected logic blocks, each including a logic circuit, an output multiplexer, and a select multiplexer. The logic circuit has an input coupled to a logic block input. The output multiplexer has first and second data inputs respectively coupled to first and second outputs of the logic circuit, a select input, and an output coupled to a logic block output. The select multiplexer has a first data input coupled to a cascade select input of the logic block, a second data input, and an output coupled to the select input of the output multiplexer. The output of the select multiplexer is also coupled to a cascade select output of the logic block. The cascade select input of the logic block is coupled to the cascade select output of an adjacent logic block.

Abstract: Circuits for implementing gating logic in a self-timed integrated circuit. An integrated circuit includes a plurality of interconnected logic blocks, each including a logic circuit and an output circuit. Each output circuit has a data input coupled to an output of the logic circuit, a gating input, and a data output coupled to an output of the logic block. The output circuit is coupled to place a value on the data input onto the data output when the gating input has a first value and the output circuit receives tokens indicating valid new data on both the data input and the gating input of the output circuit. The output circuit is coupled to leave the data output unchanged when the gating input has a second value and the output circuit receives a token indicating valid new data on both the data and gating inputs of the output circuit.

Abstract: Methods of initializing an integrated circuit (IC) in which the routing structures have data lines and handshake circuitry are provided. A node of each of the data lines is driven to a predetermined value, and the handshake circuit is disabled by disabling an acknowledge path within the handshake circuitry, e.g., by forcing all acknowledge signals in the acknowledge path to signal an acknowledgement of received data. The disablement causes the predetermined value to propagate throughout the data lines. The handshake circuitry is then enabled by enabling the acknowledge path, which releases the data lines to assume values determined by operation of the IC. When the IC is a programmable IC, configuration values may be programmed into the IC after disabling the acknowledge path and before enabling the handshake circuitry. When the handshake circuitry is enabled, the data lines assume initial values determined by the programmed configuration values.

Abstract: A device and a method for processing high data rate serial data includes a VCO initial frequency calibration circuit. The circuit includes a frequency detection block for indicating a difference between a reference clock and a divided VCO clock, a frequency calibration block that produces a digital output signal based upon the difference between the reference clock and the divided VCO clock, and a digital-to-analog converter for producing an analog VCO adjust signal. The frequency detection block produces a plurality of signals based upon the reference clock and the divided VCO clock. A plurality of user selected inputs selects a frequency detection lock range and hysteresis range and a coarse loop open calibration lock and hysteresis range. The frequency calibration block implements a state machine for producing the digital output signal that sets the initial operating frequency then adjusts the frequency of the VCO clock.

Abstract: Method and apparatus for communication between hardware blocks configured in a programmable logic device (PLD) and a computation device external to the PLD is described. A bus controller is provided for receiving words from the computation device. Each of the words includes an address component and a data component. A first-in-first-out buffer (FIFO) is configured for communication with the bus controller to store the words. A processing engine is provided having a memory space associated with the hardware blocks and being configured to receive a word at a top of the FIFO. An address decoder is provided for decoding the address component of the word at the top of the FIFO to obtain an address of a memory location in the memory space. A strobe generator is provided for coupling a strobe signal to the processing engine. The strobe signal is configured to store the word in the memory location.

Abstract: A method of generating parameters for a predistortion circuit in an integrated circuit is disclosed. The method comprises receiving, at the predistortion circuit, an input signal to be amplified by a power amplifier; receiving an output of the power amplifier at an input of the integrated circuit; comparing an output of the predistortion circuit with the output of the power amplifier; conforming the output of the power amplifier with the output of the predistortion circuit; and generating parameters to be applied to the predistortion circuit based upon the conformed output of the power amplifier and the predistortion circuit. An integrated circuit having a circuit for generating parameters for a predistortion circuit of the integrated circuit is also disclosed.

Abstract: A device control register controller for a processor block Application Specific Integrated Circuit (“ASIC”) core is described. Device control register slave blocks are coupled to the device control register controller and have access to device registers for a plurality of interfaces of the processor block ASIC core. A master device interface is for coupling at least one slave device external to the processor block ASIC core to the device control register controller. A slave device interface is for coupling a master device external to the processor block ASIC core to the device control register controller.

Abstract: Fluid-based dielectric material is used to backfill multiple patterned metal layers of an IC on a wafer. The patterned metal layers are fabricated using conventional CMOS techniques, and are IMD layers in particular embodiments. The dielectric material(s) are etched out of the IC to form a metal network, and fluid dielectric material precursor, such as a polyarylene ether-based resin, is applied to the wafer to backfill the metal network with low-k fluid-based dielectric material.

Abstract: A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.

Abstract: An integrated circuit having a circuit for reducing distortion in a power amplifier is disclosed. The integrated circuit comprises a predistortion circuit coupled to receive a signal to be amplified; sample capture buffers coupled to an output of the predistortion circuit and an input/output port of the integrated circuit; and an estimator circuit coupled to the sample capture buffers, wherein the estimator circuit generates parameters for the predistortion circuit based upon the output of the predistortion circuit and an output of the power amplifier received at the input/output port of the integrated circuit. A method of reducing distortion in a power amplifier is also disclosed.

Abstract: A programmable logic device includes a configuration memory, a checker, and a redundant-logic detector. An array of programmable logic and interconnect resources is configurable to implement a selected user design. The configuration memory stores configuration data that configures the array of programmable logic and interconnect resources to implement the specified user design. A checker calculates a sequence of checksums from the configuration data that is stored in the configuration memory. A redundant-logic detector indicates corruption of the configuration data stored in the configuration memory in response to at least two consecutive checksums in the sequence not matching a reference value.

Abstract: Testing an integrated circuit using dedicated function pins in a non-dedicated function test mode is described. In a first mode, a circuit block is activated for processing first information provided via dedicated function pins. In a second mode, the circuit block is deactivated. Control logic is coupled to receive state information from a state storing device and coupled to receive the first information and second information from the dedicated function pins. The control logic is configured to gate the second information for passage to programmable logic responsive to the state information being for the second mode. The control logic is configured to gate the first information to preclude passage to the programmable logic responsive to the state information being for the first mode.

Abstract: A method of resetting a programmable logic device (PLD) for use with hardware co-simulation can include loading a full bitstream into the PLD. The full bitstream can program the PLD with a circuit design to be used with a first simulation. The method further can include loading a partial bitstream into the PLD thereby resetting at least one component of the circuit design that does not have a reset function such that the circuit design is initialized for use in a subsequent simulation.