Abstract: A digital signal processing block with a preadder stage for an integrated circuit is described. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the preadder stage. The preadder stage includes: a first input port of a first multiplexer coupled to the control bus; a second input port of a first logic gate coupled to the control bus; a third input port of a second logic gate coupled to the control bus; and a fourth input port of an adder/subtractor coupled to the control bus.

Abstract: According to an embodiment of the invention, a method of configuring a filter in a circuit to be implemented in an integrated circuit is disclosed. The method comprises receiving a high level design of the circuit; identifying a filter in the high level design; analyzing coefficients of the filter; and transforming the filter of the high level design to a filter using a processing block of the circuit configured to accommodate a common coefficient, wherein the processing block is coupled to receive taps associated with the common coefficient. A computer program product and a circuit for configuring a filter in a circuit to be implemented in an integrated circuit are also disclosed.

Abstract: Various approaches are provided for generating an implementation of an electronic circuit design. In one embodiment, a processor-based method implements a design in an integrated circuit or IC (e.g., a programmable logic device. The method includes storing performance-variation data that represents location-based performance variations between logically-equivalent-programmable resources of the IC. The respective stored performance-variation data of at least two logically-equivalent-programmable resources of the IC are compared. The logic of the design is mapped, placed and routed on resources of the IC. The mapping, placing and routing includes, for an implementation of at least one subset of the logic of the design, selecting between the at least two logically-equivalent-programmable resources of the IC based on a result of the step of comparing respective stored performance-variation data of the at least two logically-equivalent-programmable resources.

Abstract: A method and system for generating from a high-level placement specification the layout and schematic implementation data is disclosed. In addition packaging data and a software model may also be generated. In one embodiment an array of rows and columns is formed on an integrated circuit (IC) in which all elements in a row have the same height and all elements in a column have the same width. This array, which may be displayed in a textual or spreadsheet format, forms the high-level placement specification. A software program of this embodiment converts this high-level placement specification into layout and schematic files that can be used by a commercial CAD tool to produce a file for fabrication.

Abstract: Computer-implemented methods of generating netlists for use in post-layout simulation procedures. A lookup table includes a predetermined set of features (e.g., transistors of specified sizes and shapes) supported by an integrated circuit (IC) fabrication process, with dimensions and process induced dimension variations being included for each feature. A netlist is extracted from an IC layout, the extracted netlist specifying circuit elements (e.g., transistors) implemented by the IC layout and interconnections between the circuit elements. A search pattern is run on the IC layout to identify features in the IC layout corresponding to features included in the lookup table. Circuit elements in the extracted netlist that correspond to the identified features are then modified using values from the lookup table, and the modified netlist is output. In some embodiments, the netlist extraction, search pattern, and netlist modification are all performed as a single netlist generation step.

Abstract: A circuit is implemented using a programmable logic device (PLD) that includes an array of programmable logic and routing resources. The circuit includes a processor, a configuration port, a relocatable circuit, and an interface circuit. The processor accesses an address space using read and write transactions issued on an interface bus. The programmable logic and interconnect resources are configurable via the configuration port. The relocatable circuit is implemented in a selected region within the array by configuring the programmable logic and interconnect resources in the selected region with configuration data via the configuration port. The interface circuit translates the transactions accessing a portion of the address space assigned to the relocatable circuit into a fixed address space of the relocatable circuit. The configuration data for implementing the relocatable circuit is independent of the portion of the address space assigned to the relocatable circuit.

Abstract: Methods and systems are provided for determining a characteristic of an atomic particle affecting a programmable logic device (PLD). The PLD is configured to generate a value at one or more outputs. A source generates a packet of atomic particles. The departure from the source is indicated for the packet of the atomic particles. The PLD is impacted with the packet of the atomic particles. A change is detected in the value of one or more outputs of the PLD. The change in the value of the output or outputs is a result of the impact of the PLD by one of the atomic particles from the packet. A time interval is determined between the departure of the packet of the atomic particles from the source and the change in the value of the output or outputs.

Abstract: A method of startup for a phase-locked loop (PLL) can include, at initiation of the PLL, providing a reference voltage from a startup voltage source to an input of a voltage controlled oscillator (VCO) in the PLL, wherein the reference voltage is set to a predetermined minimum voltage. The reference voltage can be stepwise increased from the predetermined minimum voltage. A frequency of a reference signal input to the PLL can be compared with a frequency of a feedback signal originating from an output of the VCO of the PLL to determine a frequency differential as the reference voltage increases. A determination can be made as to whether a convergence criterion is met according to the frequency differential. While the convergence criterion is not met, the reference voltage can be increased. When the convergence criterion is met, the reference voltage provided by the startup voltage source can be replaced with a voltage generated by an operational voltage source.

Abstract: A circuit to generate Orthogonal Variable Spread Factor (OVSF) codes for CDMA systems. The circuit includes a shift register to determine the OVSF code k for a given spread factor SF, wherein k ranges between 0 and (SF?1). A memory cell register stores the leftmost bit of the code that is loaded into the first bit of the shift register. An XOR gate provides an input to the shift register after the first bit is loaded from the memory cell. An address Look Up Table (LUT), or state machine, is connected to the shift register to select a tap output from one of the shift register bits to provide a first input to the XOR gate. A secondary OVSF code register connects to a second input of the XOR gate to provide code bits from lower SF values making up the code from the current SF value.

Abstract: A Programmable Logic Device (PLD) is provided with configuration memory cells displaying a superior soft error immunity by combating single event upsets (SEUs) as the configuration memory cells are regularly refreshed from non-volatile storage depending on the rate SEUs may occur. Circuitry on the PLD uses a programmable timer to set a refresh rate for the configuration memory cells. Because an SEU which erases the state of a small sized memory cell due to collisions with cosmic particles may take some time to cause a functional failure, periodic refreshing will prevent the functional failure. The configuration cells can be DRAM cells which occupy significantly less space than the SRAM cells. Refresh circuitry typically provided for DRAM cells is reduced by using the programming circuitry of the PLD. Data in the configuration cells of the PLD are reloaded from either external or internal soft-error immune non-volatile memory.

Abstract: Circuits and methods for a differential signal interface for coupling differential signals at a first frequency on a pair of opposite polarity signals to a multiple gigabit transceiver with generic buffers for receiving, transmitting or transceiving out of band signals at a second frequency lower than the first frequency are disclosed. Termination networks are provided coupling generic input buffers to respective ones of the pair of opposite polarity signals for receiving out of band signals where the opposite polarity signals are placed at voltages so that the differential voltage between them is below a threshold voltage. Methods for providing generic buffers with multiple gigabit transceivers for receiving and transmitting out of band signals on a differential signal interface are provided. Out of band signals are received when the out of band signaling protocol is not known.

Abstract: A coefficient labeling circuit arrangement for bitplane coding passes in embedded block coding. In one embodiment, a significance lookahead circuit generates lookahead significance states of coefficients in past, current, and future magnitude stripe slices of a code-block containing a plurality of coefficients. A plurality of context labeling circuits are coupled in parallel to the significance lookahead circuit. Each context labeling circuit is configured with a respective significance propagation pass circuit, a respective magnitude refinement pass circuit, and a respective cleanup pass circuit. Context labels are generated in parallel for all bits of the current magnitude stripe slice.

Abstract: A first wire having sidewalls of an integrated circuit is tapered from the proximal end to the distal end to reduce width from the first width to the second width. A second wire, spaced apart from the first wire, the second wire has sidewalls. The first wire and the second wire are each horizontally disposed along side each other forming a part of a sidewall capacitor between facing sidewalls. The sidewall capacitor capacitance is progressively reduced responsive to the first wire taper.

Abstract: Delay compensation is described. A clock signal used to generate a transmit clock is obtained. Clock cycles are counted to provide-a count signal associated with external device latency. The count signal is captured responsive to the clock signal.

Abstract: A linear feedback shift register (LFSR) based design is applied to cyclic redundancy check (CRC) modules, in which a CRC building block having a minimum width is implemented. The CRC building block accepts a generator polynomial as an input design parameter to build a CRC block module. The modularity of the design then allows a larger CRC block design to be constructed from multiple CRC block modules such that wider data width blocks may be accommodated. The LFSR based designs are extended to communication systems that may require scrambling and descrambling functionality.

Abstract: A non-volatile static random access memory (“SRAM”) cell using variable resistance random access memory (“RAM”) cells is described. A memory tri-cell includes an SRAM cell with a first charge node and a second charge node. A first variable resistance random access memory cell is coupled between the first charge node and a supply voltage bus. A second variable resistance random access memory cell is coupled between the first charge node and a ground bus. A first control gate is coupled between the supply voltage bus and the first variable resistance random access memory cell. A second control gate is coupled between the ground bus and the second variable resistance random access memory cell.

Abstract: Method and apparatus for processing a dataflow description of a digital processing system is described. In one example, a model of the dataflow description is simulated. Computational steps performed during the simulation and actual dependencies among the computational steps resulting from the simulation are identified. Causation trace data is generated in response to the step of recording. The causation trace data may then be analyzed using one or more analyses to produce quantitative data that characterizes the dataflow description.

Abstract: Various port reduction methods are employed to reduce the number of port definitions in a simulation file. A ground port reduction method is first employed to reduce certain power supply reference connections to an absolute ground reference for the circuit model. Next, all commonly defined port definitions are combined into a single port definition. Finally, a current analysis is used to further reduce the number of port definitions in the simulation file by removing the current return ports from the simulation file.

Abstract: A circuit may be used for testing for faults in a programmable logic device. The circuit may include a clock generator coupled to receive a reference clock signal and generate a high speed clock signal; a circuit under test coupled to receive selected pulses of the high speed clock signal; and a programmable shift register coupled to receive a pulse width selection signal and generate an enable signal for selecting the pulses the high speed clock signal, wherein the pulse width of the enable signal is selected based upon the value of the pulse width selection signal. A method of testing for faults in a programmable logic device is also disclosed.

Abstract: A method for providing placement based configurations in integrated circuits and integrated circuits having configurable data files for logic blocks based on the location of the blocks therein are disclosed. Location information for at least one logic block in an integrated circuit is identified. A configuration data file for configuring the at least one logic block in the integrated circuit is generated based on the identified location of the at least one logic block.