Abstract: A method of co-simulation involving a high level modeling system and an integrated circuit such as, e.g., a programmable logic device (PLD) can include, when writing to at least one input port of the PLD, storing a plurality of commands from a co-simulation engine within a command buffer and, responsive to a send condition, sending the plurality of commands to the PLD as a single transaction. When reading from at least one output port of the PLD, selectively reading from a cache external to the PLD or a memory of the PLD according to a state of cache coherency.

Abstract: A method of generating a plurality of data streams using a data protocol is disclosed. The method comprises steps of receiving an input data stream comprising a periodic sequence of data words, wherein each the data word of the input data stream is associated with a data stream of a plurality of data streams. The data words of the input data stream are sequentially processed by a data control circuit. Finally, data output by the data control circuit is demultiplexed to generate a plurality of output data streams. A circuit for generating a plurality of data streams using a data protocol is also disclosed.

Abstract: An integrated circuit device is described. In particular, the integrated circuit comprises a substrate comprising active devices; a plurality of metal layers formed over the substrate, the plurality of metal layers being separated by insulating layers; a plurality of vias enabling connections to the active devices of the substrate; a contact pad support structure defining an opening in a metal layer of the plurality of metal layers and being coupled to an interconnect line; and a contact pad formed over the contact pad support structure. A method of implementing a contact pad in an integrated circuit is also disclosed.

Abstract: A method for scheduling channel usage for an over-the-air (“wireless”) network downlink is described. Information associated with incoming traffic and outgoing traffic to a node as associated with user equipment is obtained. The user equipment is capable of establishing a communication link with the node. The information obtained is placed in respective queues, which are each associated with the user equipment. A count level of the queues is obtained. An interval rate for the incoming traffic is determined. A receive rate for the user equipment is obtained. An incoming average rate for the incoming traffic is determined. An outgoing average rate for the outgoing traffic is determined. A proportion value is generated responsive to the incoming average rate, the outgoing average rate, the receive rate, and the interval rate.

Abstract: Methods and apparatus for implementing a stacked memory-programmable integrated circuit system-in-package are described. An aspect of the invention relates to a semiconductor device. A first integrated circuit (IC) die is provided having an array of tiles that form a programmable fabric of a programmable integrated circuit. A second IC die is stacked on the first IC die and connected therewith via inter-die connections. The second IC die includes banks of memory coupled to input/output (IO) data pins. The inter-die connections couple the IO data pins to the programmable fabric such that all of the banks of memory are accessible in parallel.

Abstract: Apparatus and method for outputting data from an integrated circuit having programmable logic for Single-Event Upset tolerant operation is described. Configuration memory associated with the programmable logic is read. Bits of the configuration memory read are error checked. Buffers are cycled to select one to load and another one to unload responsive to completion of each error checking cycle of the bits. For a cycle of the error checking, a first data portion is loaded into one buffer of the buffers for the cycle, it is verified whether the bits are valid for the cycle, and a second data portion is unloaded from another buffer of the buffers responsive to the bits being valid for the cycle.

Abstract: A method and apparatus is provided that facilitates low-power consumption during a suspend mode of operation of an integrated circuit (IC), while substantially eliminating current paths within the IC that may be created should any of the power supplies be deactivated during the suspend mode. Deactivation of one or more power supplies during a normal mode of operation is also facilitated, whereby current paths created by the deactivated power supplies are also eliminated. Voltage bias circuitry is added to certain voltage regulators within the IC, so as to maintain those voltage regulators inactive due to a drop in voltage magnitude that is sensed when one or more power supplies are disabled. In addition, a well bias circuit is employed to maintain the substrate bias potential of certain devices within the voltage regulators and associated amplifiers to a fixed potential depending upon the operational mode of the IC.

Abstract: A semiconductor device having structures for reducing substrate noise coupled from through die vias (TDVs) is described. In one example, a semiconductor device has a substrate, at least one signal through die via (TDV), and ground TDVs. The substrate includes conductive interconnect formed on an active side thereof. The conductive interconnect includes ground conductors and digital signal conductors. Each signal TDV is formed in the substrate and is electrically coupled to at least one of the digital signal conductors. The ground TDVs are formed in the substrate in a ring around the at least one signal TDV. The ground TDVs are electrically coupled to the ground conductors. The ground TDVs provide a sink for noise coupled into the substrate from the signal TDVs. In this manner, the ground TDVs mitigate noise coupled to noise-sensitive components formed on the substrate.

Abstract: Phase-to-sinusoid conversion and method for direct digital synthesis are described. At least one quadrant of values for a sinusoidal signal are real-to-finite bit resolution mapped to provide preconditioned values which are on average shifted down by half of a LSB position. The at least one quadrant of preconditioned values are stored in a lookup table. MSBs of a phase-accumulated signal are used as an address for accessing from the lookup table a sinusoid value. At least a logic 1 is added as an LSB to an interim output associated with the sinusoid value to provide an adjusted sinusoid value having a bit width greater than that of the sinusoid value to provide a digitally synthesized sinusoidal value.

Abstract: Lane configuration of an interface device of an integrated circuit is described. A core is used to tile a portion of an integrated circuit with a first version of the core and a second version of the core. The core is an application specific circuit version of an interface device. The first version and the second version in combination have a sharable interface. Each of the first version and the second version has N lanes. The first version is a primary version and the second version is a secondary version responsive to a shared interface mode. The N lanes of the second version are combined with the N lanes of the first version via the sharable interface for providing 2-by-N lanes of input/output to the first version.

Abstract: Method and apparatus for configuring a processor embedded in an integrated circuit for use as a logic element is described. In one example, a processing apparatus in an integrated circuit includes a point-to-point data streaming interface and arithmetic logic unit (ALU) circuitry. The ALU circuitry includes at least one input port in communication with the point-to-point data streaming interface. The processor may also include a register file and multiplexer logic. The multiplexer logic is configured to selectively couple the register file and the point-to-point streaming interface to the at least one input port of the ALU circuitry.

Abstract: Composite flip-chip with encased components and method of fabricating the same is described. One aspect of the invention relates to fabricating composite flip-chip packages for integrated circuit dice. Interposing substrates are formed. At least one discrete component is attached to a bottom surface of each of the interposing substrates. A first array of solder balls is placed on the bottom surface of each of the interposing substrates. The interposing substrates are mounted to a carrier strip. The integrated circuit dice are attached to top surfaces of the interposing substrates. The integrated circuit dice and the interposing substrates are encapsulated in molding compound to define flip-chip assemblies.

Abstract: A model and method are provided for lowering device jitter by controlling the stackup of PCB planes so as to minimize inductance between a FPGA and PCB voltage planes for critical core voltages within the FPGA. Furthermore, a model and method are provided for lowering jitter by controlling the stackup of package substrate planes so as to minimize inductance between a die and substrate voltage planes for critical core voltages within the die.

Abstract: A method and apparatus to implement clock signal adaptation is provided to characterize an input clock signal that is to be adapted and in response, generate adaptation updates at each subsequent clock cycle of the input clock signal. In a first embodiment, clock signal adaptation occurs through duty cycle correction (DCC) to substantially achieve a 50% duty cycle. In an alternate embodiment, clock signal adaptation occurs through a multiplication operation that is applied to the clock signal to be adapted, whereby the multiplication operation is parameterizable to allow odd/even multiplication. In an alternate embodiment, clock signal adaptation occurs through a phase-shift operation that is applied to the clock signal to be adapted, whereby the phase-shift operation is parameterizable to allow all possible fractions and percentages of phase shifts.

Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

Abstract: Method and apparatus for encoding configuration data is described. An integrated circuit device having a configuration interface is coupled to boot memory coupled at the configuration interface. The boot memory contains boot cores for configuring the integrated circuit device via the configuration interface. The boot cores include a configuration encoder core and an internal processor interface core. The boot cores may further include a processor core. The configuration encoder core provides a peripheral interface internal to the integrated circuit device, and the boot memory contains at least one set of instructions for encoding configuration data read from configuration memory. The encoded configuration data may be sent via the peripheral interface. Alternatively, configuration encoder core may include a configuration bitstream for instantiating an encoder in configurable resources for encoding readback configuration data.

Abstract: A MOS transistor is used as a programmable three-terminal non-volatile memory element. The gate dielectric layer of the MOS transistor has a first portion with a relatively higher dielectric breakdown strength than a second portion. The location of the second portion is chosen so as to avoid having the gate dielectric layer break down near the edge of the active area or isolation area during programming. In a particular embodiment, the gate dielectric layer is silicon oxide, and the first portion is thicker than the second portion.

Abstract: Individual storage locations in a PROM that stores a configuration file for a PLD may be directly addressed so that selected portions of the data stored therein may be replaced or updated with new data without having to erase all the contents of the PROM, reprogram the PROM with a new configuration file, and/or reconfigure the FPGA with the new configuration file. For some embodiments, a PROM includes a JTAG-compatible interface that is coupled to a JTAG-compatible test circuit provided within the PLD, and circuit within the PLD is configured to directly address individual storage locations in the PROM via the PROM's JTAG interface using well-known JTAG commands.

Abstract: Within an Electronic Design Automation (EDA) tool, a method of macro inference can include translating a hardware description language (HDL) template into a macro template and translating a circuit design into a format corresponding to the macro template. The method further can include matching a portion of the translated circuit design with the macro template and replacing the portion of the circuit design matching the macro template with a macro associated with the macro template. The resulting updated circuit design is then output, e.g., to a user, a computer file, or another EDA tool.

Abstract: A method and system for a programmable input/output transceiver is disclosed. A circuit in accordance with the invention includes a programmable transceiver. The programmable transceiver is configured and/or controlled to support an interface standard. A system according to the present invention includes a programmable transceiver and a field-programmable gate array (FPGA) core coupled to program the programmable transceiver.