Abstract: A computer-implemented method of balancing logic resource usage in a circuit design for a programmable logic device (PLD) can include determining that an assignment of elements of the circuit design to a first type of logic resource of the PLD is unbalanced compared to an assignment of elements of the circuit design to an alternate type of logic resource of the PLD. An Integer Linear Programming (ILP) formulation specifying a balanced assignment of elements to the first and alternate types of logic resources can be generated. A solution for the ILP formulation can be obtained. Selected elements of the circuit design can be re-mapped from the first type of logic resource to the alternate type of logic resource according to the solution of the ILP formulation and the circuit design specifying the re-mapped elements can be output.

Abstract: Methods are provided for generating a hardware description language (HDL) specification of a network packet processor from a first, second, and third specification. The first specification specifies at least one handler of the network packet processor for processing input network packets and producing output network packets. Each handler processes a corresponding type of network packets and includes one or more actions for inspecting and modifying fields of the corresponding type of network packets. The second specification specifies a plurality of characteristics of a plurality of ports of the network packet processor. The characteristics include respective data widths of the ports. The ports include one or more input ports for receiving the input network packets and one or more output ports for transmitting the output network packets. The third specification specifies one or more behavioral constraints of the network packet processor.

Abstract: A method of automatically generating multithreaded datapaths from a circuit description can include identifying a plurality of process threads from a circuit description, wherein each process thread comprises at least one function, and representing each of the plurality of process threads as an order of operations graph including nodes that correspond to functions and edges that indicate dependencies between the functions. The method also can include identifying at least one conditional edge from the order of operations graphs. An updated circuit description can be generated that specifies a multiplexer for each conditional edge.

Abstract: The circuits and methods of the various embodiments of the present invention enable changing the frequency of a frequency synthesizer. According to one embodiment, a method of changing a frequency of a clock signal generated by a frequency synthesizer comprises the steps of receiving a reference clock signal; receiving a command comprising a new frequency synthesizer value; locking to a new frequency based upon the new frequency synthesizer value; and dynamically outputting a generated clock signal based upon the new frequency synthesizer value. According to another embodiment, a method of changing a frequency of a clock signal comprises adaptively adjusting the digital loop bandwidth of the frequency synthesizer. A circuit for changing a frequency of a clock signal generated in an integrated circuit is also disclosed.

Abstract: Various embodiments of the invention provide a method for transferring communication data through one or more pins of a programmable logic device (PLD). The PLD includes a configuration port that may be used to program programmable logic and interconnect resources of the PLD. The programmable logic and interconnect resources include the input/output blocks of the PLD. Portions of the communication data are sequentially transferring between certain pins of the PLD and certain input/output registers in one or more input/output blocks associated with the pins. A frame of configuration data including a portion of the communication data is transferred between the input/output registers and a frame register of the configuration port of the PLD. Formats are converted between the portion of the communication data and the frame of the configuration data in the frame register of the PLD.

Abstract: An Ethernet co-simulation interface for use with a software-based simulation tool and a design under test disposed on a programmable device can include a host interface and a network processor. The host interface can execute on a host computing system and facilitate data transfer between the software-based simulation tool and a communication link to the design under test. The network processor can be implemented within the programmable device and facilitate data transfer between the communication link and the design under test. The host interface and the network processor can exchange simulation data formatted as raw Ethernet frames over a point-to-point Ethernet connection.

Abstract: An output circuit providing an adjustable output amplitude and common-mode voltage is described. The output circuit includes at least one driver circuit and a common-mode feedback circuit including a first replica circuit of the at least one driver circuit. The common-mode feedback circuit is coupled to receive a first bias and provide an output coupled to the at least one driver circuit. The output circuit may also include a current circuit having a configurable resistor and a second replica circuit of the at least one driver circuit. The current circuit may be coupled to receive a second bias and to provide an output coupled to the at least one driver circuit and the common-mode feedback circuit.

Abstract: A static random access memory (“SRAM”) has a plurality of SRAM cells connected to a word line. A static noise margin (“SNM”) detector controls a pull-down transistor that selectively couples the word line to a ground path. The SNM detector is configured to produce a first output signal in response to a SNM event that couples the word line to the ground path, and otherwise produces a second output signal that de-couples the word line from the ground path.

Abstract: A method of placing a circuit design can include selecting one or more candidate mobile nodes from a plurality of overlapped nodes of the circuit design and determining a gain region for each candidate mobile node. The method also can include assigning the candidate mobile node to a site within a gain region according to a cost function. The gain region is associated with the candidate mobile node. The method further can include iteratively selecting and assigning candidate mobile nodes according to a measure of overlap for the circuit design.

Abstract: A method of testing a semiconductor wafer having a test structure performs an E-beam stress scan of the test structure in an E-beam system to electrically stress the test structure to produce a stress defect. An inspection scan is performed in the E-beam system to identify the stress defect.

Abstract: Integrated circuits (ICs) having bus-based programmable interconnect structures are provided. An IC includes substantially similar logic blocks and a programmable interconnect structure programmably interconnecting the logic blocks. The programmable interconnect structure includes bus structures and programmable switching structures programmably interconnecting the bus structures. Each bus structure includes N data lines, where N is an integer greater than one, and N commonly controlled storage elements (e.g., latches) for storing data on the N data lines. In some embodiments, at least one of the bus structures includes handshake logic, including a C-element coupled to drive a ready line, to receive an acknowledge line, and to provide a control signal to each of the N storage elements in the bus structure.

Abstract: A configurable interface for an integrated circuit is described. The integrated circuit includes a first core, where the first core is an application specific circuit version of a Peripheral Component Interconnect Express (“PCIe”) interface device. First configuration memory cells are associated with the first core, and the first configuration memory cells are for configuring the first core. The first configuration memory cells are programmable responsive to a first portion of a configuration bitstream, and the configuration bitstream is capable of including user-logic information for programming programmable logic of the integrated circuit.

Abstract: A method of employing memory cells of an integrated circuit is disclosed. The method comprises steps of storing configuration data in a plurality of memory cells of a memory of the integrated circuit; selecting unused memory cells of the memory of the integrated circuit for use as a scratchpad memory; providing access to the unused memory cells of the integrated circuit; and enabling use of the unused memory cell of the integrated circuit in a user mode as scratchpad memory. According to one embodiment of the invention, a plurality of input/output ports of the integrated circuit is coupled to a plurality of JTAG inputs coupled to the plurality of unused memory cells. A programmable logic device having memory cells for storing data, and a circuit employing a programmable logic device, are also disclosed.

Abstract: A test methodology for testing a memory device with a RSR feature is disclosed. For example, a method for testing a memory device having at least one memory cell group, at least one redundant memory cell group, and a defect detect register is disclosed. In one embodiment, the method applies at least one memory test to the at least one memory cell group; and applies a defect detect register test to the defect detect register.

Abstract: An integrated circuit operable to wirelessly communicate with other devices by utilizing a radio transceiver and a routing element is disclosed. The routing element is operable to route a signal between various circuit elements and is selectively operable to function as an antenna when coupled with the radio transceiver.

Abstract: An output circuit allows the slew rate of its output signal to be selectively adjusted. The output driver circuit includes an output driver and pre-driver circuits. The output driver includes an output transistor coupled between a first supply voltage and the output terminal. The pre-driver circuit selectively adjusts a series resistance between the output transistor's gate and a second supply voltage in response to mode control signals.

Abstract: Method and apparatus for peak-to-amplitude ratio reduction are described. A data carrying signal waveform with sub-carrier signals (S1-1 through S1-M) is obtained. An initial peak reduction waveform (S2(m)) is obtained by selection of a portion of the sub-carrier signals (S1-1 through S1-M) for non-data carrying. The initial peak reduction waveform (S2(m)) is refined by at least one recursive iteration which combines the initial peak reduction waveform (S2(m)) with a circularly time-shifted version thereof to obtain a resultant peak reduction waveform having a peak side lobe amplitude less than that of the initial peak reduction waveform (S2(m)).

Abstract: A method of accessing, from a host application written in a first programming language, a subroutine written in a second programming language can include serializing input data expressed as an XTable formatted in a first programming language into a string representation of the input data. The method further can include de-serializing the string representation of the input data as an XTable formatted in the second programming language and executing the subroutine, wherein the XTable formatted in the second programming language is processed as input. Output data returned from the subroutine that is expressed as an XTable formatted in the second programming language can be serialized into a string representation of the output data. The string representation of the output data can be de-serialized into an XTable formatted in the first programming language.

Abstract: A method is provided to automatically allocate resources of an integrated circuit (IC) to form multipliers in a given design to optimize the use of IC resources. Information about the multipliers in the design is extracted to place the multipliers into a priority order. The priority allows primitives in the IC, like DSP blocks LUTs or MUXCYs to be economically allocated to the multipliers. The ordering criteria can include: (1) a user defined criteria, (2) the number of primitives required to implement a multiplier, or (3) a size of the multiplier operands. This invention further optimally allocates LUTs and MUXCYs when DSP48 blocks are exhausted. The steps for generating a multiplier include: constructing a partial product matrix and minimizing the adders used in the multiplier by minimizing the size of support for the partial products. Either LUTs or MUXCYs are selected depending on the size of support determined.

Abstract: A configuration management system is disclosed. For example, an embodiment of the present invention provides a configuration management system comprising a configuration storage device containing configuration data, and an integrated circuit, coupled to the configuration storage device, where the integrated circuit comprising at least one configuration management controller for managing a configuration of the integrated circuit in accordance with the configuration data, where the integrated circuit is deployed in a radiation tolerant device.