Abstract: Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock signal having a frequency that differs from the frequency of the output clock signal. The frequency of the output clock signal is a product from multiplying the frequency for the input signal and an integer ratio. The circuit includes an accumulator, a fractional phase detector, and a loop filter. The accumulator periodically adds a numerical offset value to a numerical phase value. The output clock signal is generated from this numerical phase value. The fractional phase detector generates from the numerical phase value a respective numerical phase error for each of the transitions of the input signal. The loop filter generates the numerical offset value from a filtering of the respective numerical phase errors.

Abstract: A circuit of an integrated circuit for receiving video data having a plurality of data streams of pixel data and a pixel clock is disclosed. The circuit comprises a plurality of data recovery circuits, each data recovery circuit coupled to receive a corresponding data stream of the plurality of data streams and having a phase shifter generating a clock signal used to receive the data stream; and a channel deskew circuit coupled to receive the output of each data recovery circuit and the pixel clock. A method of receiving video data is also disclosed.

Abstract: A method and system for pipelined decryption is disclosed. One embodiment includes a circuit having an iterative calculation section and a cipher text storage section in support of cipher block chaining (CBC) encryption mode. The iterative calculation section may be pipelined and configured to process multiple ciphertexts at once for increased throughput.

Abstract: A method of enabling variable latency data transfers in an electronic device, such as an FPGA with an embedded processor, is described. According to one aspect of the invention, a method comprises steps of providing an address for a data transfer between a memory controller and a peripheral device; coupling an address valid signal to the peripheral device; transferring the data between the memory controller and the peripheral device; and receiving a data transfer complete signal at the memory controller. According to another aspect of the invention, an integrated circuit enabling a variable latency data transfer is described. The integrated circuit comprises peripheral device; a memory controller coupled to the peripheral device; an address valid signal coupled from the memory controller to the peripheral device; and a transfer complete signal coupled from the peripheral device to the memory controller.

Abstract: A system for configuring a plurality of programmable devices may include an external memory, a master programmable device, and at least one slave programmable device. The programmable devices may have a parallel data bus connected in a daisy chain fashion. The programmable devices may further include a chip select signal that is also connected in a daisy chain. Special instructions embedded in the configuration bitstream, which may be stored in the external memory, are used by the programmable devices to control the configuration process.

Abstract: A receiver has a first input port and a second input port both coupled to a differential amplifier through first and second input capacitors. A bias circuit coupled to the core side of the first input capacitor and to the core side of the second input capacitor is configured to provide a selected voltage to at least one of the first input and the second input of the differential amplifier. In one embodiment, a common mode bias circuit provides a common mode voltage to both inputs of a differential amplifier. In a particular embodiment, a run length detector monitors the output of the differential amplifier and provides a run length feedback signal or an average bit density feedback signal to the set the selected voltage between periods of data reception.

Abstract: A method of implementing a circuit design can include selecting the circuit design to be implemented, wherein the circuit design comprises a plurality of partitions, and receiving a user input specifying a value of a partition property. The partition property can be associated with a selected one of the plurality of partitions of the circuit design. The method also can include performing an incremental implementation flow upon the circuit design for implementation by, at least in part, selectively modifying portions of a prior implementation of the selected partition in accordance with the value of the partition property.

Abstract: Structures and methods of efficiently implementing power management in integrated circuits (ICs). An IC includes columns of logic blocks and columns of power management blocks (PMBs). The columns of PMBs and logic blocks are placed alternately across the IC, with each PMB being coupled to a logic block in an adjacent column, and the logic blocks are coupled to each other across the columns of PMBs. The PMBs can be implemented, for example, using power gates coupled between a global power rail (either ground or power high) and a local power rail specific to the associated logic block. A PMB can be selected from a library of interchangeable PMBs based on power and performance requirements of a target application. Because the PMB is designed as a separate block, any of the interchangeable PMBs in the library can readily be included in the IC.

Abstract: Dynamic cache architecture for a multi-processor array. The system includes a plurality of processors, with at least one of the processors configured as a parent processor, and at least one of the processors configured as a child processor. A data cache is coupled to the parent processor, and a dual port memory is respectively associated with each child processor part and parcel of a unified memory architecture. The parent processor may then dynamically distribute sub-cache components to dual-port memories based upon a scatter-gather work unit decomposition pattern. A parent cache controller reads, in response to a memory request from a child processor and an address translation pattern from the parent processor, a set of data from non-contiguous addresses of the data cache according to the address translation pattern, and writes the set of data to contiguous addresses of the dual port memory associated with the requesting child processor.

Abstract: Apparatus and method for a microcontroller are described. The microcontroller includes a microprocessor having storage and bussing for accessing the storage. A portion of the bussing is coupled to hardwired operation codes, and a portion of the storage is for storing code. The hardwired operation codes are in part for placing the microprocessor into an exception handling mode. The exception handling mode includes reactivating the storage for execution of the code without having to reload the code therein.

Abstract: Methods of enabling the use of defective programmable devices. The method comprises performing functional testing for each programmable device of a plurality of programmable devices; identifying each programmable device of the plurality of programmable devices having a defective portion of programmable blocks; identifying, for each programmable device which is identified to have a defective portion of programmable blocks, a location of the defective portion; and storing, for each programmable device which is identified to have a defective portion of programmable blocks, the location of the defective portion on the programmable device.

Abstract: SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array.

Abstract: A method of processing data input to a first-in first-out memory is disclosed. The method comprises steps of receiving input data words from a pipeline stage at an input of the first-in first-out memory; receiving data valid bits associated with the pipeline stage; generating a count associated with the data valid bits; and coupling the count to the first-in first-out memory. The step of generating a count associated with the data valid bits may comprise encoding the data valid bits to generate a valid data word representing the number of pipeline stages having valid data. The method of further comprises a step of generating an almost full signal based upon the count, and in particular generating an almost full signal when a read pointer incremented by the count of valid bits in the pipeline stages equals a write pointer. A circuit for processing data is also disclosed.

Abstract: A method and apparatus for reducing parasitic capacitance. A P-well blocked layer is formed directly beneath a parasitic device. The P-well blocked layer significantly increases the resistance underneath the parasitic device. The resistance of the P-well blocked layer, in effect, partially disconnects the parasitic device from the ground terminal to minimize the effective capacitive impedance that is added to the total termination impedance.

Abstract: The methods and circuits of the present invention relate to testing integrated circuits. According to one aspect of the invention, a method of testing an integrated circuit is disclosed. The method comprises the steps of coupling test equipment to the integrated circuit; coupling a test equipment clock signal from the test equipment to the integrated circuit, wherein the test equipment clock signal has a first frequency; generating an internal burst clock signal within the integrated circuit based upon the test equipment clock signal, wherein the internal test clock signal has a burst frequency; and testing the integrated circuit using the internal burst clock signal. Other methods and circuits for testing programmable logic devices are also described.

Abstract: A method, apparatus and program storage device that provides an error correction code memory system with a small footprint and byte write operation. A memory controller virtualizes the memory controller interface, multiplexes ECC data onto the same pins as data, and stores replicated ECC data structures interleaved with data in system memory. These mechanisms enable a range of very cost effective small memory subsystems that support ECC operation in a minimum of standard commodity memory devices. ECC encoding is provided to support efficient byte write operations.

Abstract: A method (100) of translating an imperative language function into a parameterized hardware component can include the steps of using (102) formal imperative function arguments to represent at least one among a component input port and a component parameter and distinguishing (104) between formal imperative function arguments intended as component parameters from formal imperative function arguments intended as component input ports. The method can generate (106) hardware description by providing a framework where imperative language functions can be translated into hardware components by being instantiated, combined and simulated. Arbitrary code can be associated (108) to a function-importing block as parameterization code and enabling an assignment of arbitrary code to actual imperative function arguments. The arbitrary code can be executed (110) in an interpreter that analyzes assigned variables by name and compares variable names with the formal argument identifiers in an imported function.

Abstract: A PLD is configurable to efficiently implement a wide variety of user functions. The PLD includes a programmable interconnect circuit, programmable logic circuits, one-bit registers, selector circuits, and input/output blocks. The programmable interconnect circuit is configurable to connect the signal lines of its output ports to the signal lines of its input ports. The programmable logic circuits are configurable to implement a programmable function generating one-bit signal values from a respective output port of the programmable interconnect circuit. The one-bit registers store a respective one of these one-bit signal values. The programmable selector circuits are each coupled to output ports of a plurality of the one-bit registers, with each of these one-bit registers coupled to a respective one of the programmable logic circuits.

Abstract: An apparatus for interconnecting stacked dice on a programmable integrated circuit is described. In one example, an integrated circuit die comprises a programmable integrated circuit that includes first and second interface tiles. The first interface tile is in electrical communication with a first array of pins on the integrated circuit die, and the second interface tile is in electrical communication with a second array of pins on the integrated circuit die. At least one dedicated routing resource is formed on the integrated circuit die between the first interface tile and the second interface tile. The at least one dedicated routing resource is configured to couple at least one pin of the first array of pins to at least one pin of the second array of pins.

Abstract: Method and apparatus for module design in a PLD is described. In one example, a PLD includes a reconfigurable module, a static module, and at least one logic interface macro. The reconfigurable module includes a signal interface and is configured for active partial reconfiguration. The static module includes a signal interface. Each logic interface macro includes first pins coupled to the signal interface of the reconfigurable module and second pins coupled to the signal interface of the static module. The first pins and the second pins are disposed in an implementation area of the reconfigurable module. In one embodiment, each logic interface macro includes a slice of a configurable logic block (CLB). In some embodiments, each logic interface macro is implemented using another type of logic block, such as a block RAM and/or multiplier block.