Abstract: An input/output (I/O) structure includes a delay element usable for the input path, the output path, or both input and output paths in a user design. In a first mode, the delay element is included in the input path. In a second mode, the delay element is included in the output path. In a third mode, the I/O structure includes the delay in both outgoing signal paths and incoming signal paths, e.g., by utilizing an output tristate signal to control the direction of the delay line. When the output buffer is driving, the delay is inserted in the output path. When the output buffer is tristated, the delay is inserted in the input path. Thus, a single delay element is dynamically shared by both input and output signals that use the same I/O pad. In an optional fourth mode, the delay element is bypassed by both input and output signals.

Abstract: A method of placing circuit elements of a partitioned circuit design on a target programmable logic device (PLD) can include mapping circuit elements of the circuit design to corresponding partitions of the circuit design, selecting a circuit element of the circuit design, and selecting a candidate location within a logic boundary on the target PLD. The method also can include validating the candidate location for the selected circuit element, at least in part, according to whether the selected circuit element belongs to a same partition of the circuit design as at least one other circuit element already placed within the logic boundary. The selected circuit element can be selectively placed at the candidate location according to the validation.

Abstract: Method of informing a processor that a coprocessor instruction is not executable by a coprocessor is described. The coprocessor, instantiated in configurable logic, is configured to execute a subset of coprocessor instructions, excluding user-selected instructions not instantiated. The processor is coupled to the coprocessor via a controller. The coprocessor instruction is sent from the processor to the controller, which queries control logic to determine whether the coprocessor is configured to execute the coprocessor instruction. If a control bit is set to disable an instruction or group of instructions, the coprocessor instruction is not executable by the coprocessor.

Abstract: Semiconductor assemblies having reduced thermal spreading resistance and methods of making the same are described. In an example, a semiconductor device includes a primary integrated circuit (IC) die and at least one secondary IC die mounted on the primary IC die. A heat extraction element includes a base mounted to the semiconductor device such that each of the at least one secondary IC die is between the primary IC die and the heat extraction element. At least one dummy fill is adjacent the at least one secondary IC die, and each thermally couples the primary IC die to the heat extraction element.

Abstract: At least one MOS parameter of a MOS fuse is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse is programmed by applying a programming signal to the fuse terminals so that programming current flows through the fuse link. The fuse resistance is measured to provide a measured fuse resistance associated with a first logic value. A MOS parameter of the programmed MOS fuse is measured to provide a measured MOS parameter value. The measured MOS parameter value is compared to the reference MOS parameter value to determine a second logic value of the MOS fuse, and a bit value is output based on the comparison.

Abstract: A processor-implemented method is provided for constructing a model of a programmable logic device (PLD) design. A netlist is input that describes the PLD design. An identification is input of programmable tile modules that include a programmable resource, which is either programmable interconnect or programmable logic. A first characterization data is input for sub-modules of the programmable tile modules for the programmable resource. For each programmable tile module, the routing arcs of each programmable interconnect are generated. A second characterization data is input for a configuration memory cell module of the PLD design. A third characterization data is input for a configuration control module of the PLD design. A first map is generated that links each routing arc to a bit of configuration data for programming the programmable interconnect. A second map is generated that links each logic function to a bit of configuration data for programming the programmable logic.

Abstract: Method and apparatus for transmission of information is described. A first transceiver has transmitter reconfigurable logic and a second transceiver has receiver reconfigurable logic. The first transceiver communicates with the second transceiver via a communication channel. The transmitter reconfigurable logic is configured to transmit preamble information and to receive a measurement of the preamble information. The receiver reconfigurable logic is configured to measure the preamble information and to transmit the preamble information measured. The preamble information is communicated via the first transceiver to the second transceiver via the communication channel. The receiver reconfigurable logic of the second transceiver measures the preamble information communicated. The measurement of the preamble information is sent via the receiver reconfigurable logic of the second transceiver to the first transceiver via the communication channel.

Abstract: Method and apparatus for testing input/output circuits of an integrated circuit are described. An integrated circuit includes input/output circuits having input/output pads. The input/output pads are capable of being coupled together to a tester channel. The input/output circuits each are configurable via configuration circuitry to be in either a first mode or a second mode responsive to a select circuit of the configuration circuitry coupled to receive a first input for the first mode and a second input for the second mode. The select circuit is controlled responsive to a control select signal common to all or a portion of the select circuits of each of the input/output circuits.

Abstract: Method and apparatus for block boundary detection is described. A signal is received. The signal is quantized to provide a quantized signal to at least one correlator, the quantized signal being a sequence of samples. The sequence of samples and a reference template including totaling partial results from the at least one correlator are cross-correlated to provide a result, the result being a symbol timing synchronization responsive to the cross-correlation also known as block boundary detection. The cross-correlation is provided in part by combining by exclusive-ORing a regression vector obtained from the sequence of samples and a coefficient term vector obtained from the reference template.

Abstract: Partial reconfiguration of programmable logic for supporting a Multiple-input, Multiple-Output Orthogonal Frequency Division Multiplexing (“MIMO-OFDM”) communication system is described. A PHY block in a programmable device may be instantiated generally in part in programmable logic of the programmable device. Control information is obtained for a network node when deployed and/or from a wireless transmission of a packet or frame, which is demodulated in the PHY block. Responsive to the control information demodulated, bitstream information is obtained to configure the portion of the PHY block using the programmable logic of the programmable device.

Abstract: A PLD includes a plurality of logic blocks, a test circuit, and a test pin set. The logic blocks are coupled to gating circuits that selectively adjust an operating voltage for the blocks in response to control signals. During operation of the PLD, the control signals are updated in response to externally-generated signals provided to the PLD via the test pin set and routed to the logic blocks using the test circuit.

Abstract: A server system for receiving and processing manufacturing data from a plurality of semi-conductor manufacturers is disclosed. The server system includes: a file capture module for receiving the manufacturing data from the plurality of semi-conductor manufacturers; a format conversion module coupled to the file capture module, the format conversion module converting the manufacturing data to a standard database format for storage in a database; a query builder module coupled to a client web browser for interactively changing contents of the client web browser depending upon a plurality of client selections on the client web browser, the query builder module configured to build a final query based on the plurality of client selections; and a report generation module coupled to the database and the query builder module, the report generation module generating a report based on the final query.

Abstract: A method of minimizing power consumption in an integrated device is disclosed. The method comprises providing a plurality of circuit blocks having circuits for performing logic functions, wherein each circuit block consumes power in a static state; coupling one of a plurality of operating voltages to each circuit block of the plurality of circuit blocks; enabling a reduction of power consumed by a first set of circuit blocks by way of a first power reduction signal; and enabling a reduction of power consumed by a second set of circuit blocks by way of a second power reduction signal. A circuit for minimizing power consumption in a device is also disclosed.

Abstract: A method of generating an output of a frequency synthesizer is disclosed. The method comprises the steps of generating an output of the frequency synthesizer based upon frequency synthesizer values and a reference clock signal; receiving a command comprising a first new frequency synthesizer value; locking to a new frequency based upon the first new frequency synthesizer value; and simultaneously loading a second new frequency synthesizer value while locking to the new frequency. A circuit for generating an output of a frequency synthesizer is also disclosed.

Abstract: A method and apparatus is provided to significantly increase the flexibility of readback capture mechanisms, the apparatus being an integrated circuit device, comprising a configuration data router coupled to receive at least one configuration data frame from a configuration interface, a configuration memory space coupled to the configuration data router and adapted to receive the configuration data frame to define a user logic block and a capture block within the programmable logic device, the user logic block including, a monitor control block coupled to the capture block and adapted to report activity within the user logic block to the capture block, and a configuration control logic block coupled to the capture block that is adapted to assert the capture signal in response to the asserted alert signal.

Abstract: A method of configuring an integrated circuit having programmable logic including the steps of generating a configuration bitstream in accordance with a configuration setup, storing the configuration bitstream into a portion of a memory, configuring the programmable logic of the integrated circuit with a first configuration portion of the configuration bitstream of the memory, monitoring the integrated circuit for at least one configuration error generated in response to an event upset, reconfiguring at least a portion of the programmable logic of the integrated circuit with a second configuration portion of the configuration bitstream in response to the at least one configuration error generated. The integrated circuit may operate normally during the process of reconfiguring the at least a portion of the programmable logic.

Abstract: A method of configuring a device having programmable logic is disclosed. The method comprises storing instructions in the device; selecting between one of the instructions stored in the device and an instruction coupled to an input/output port of the device; coupling the instruction to a non-volatile memory; and reading a configuration bitstream from the non-volatile memory based upon the selected instruction. A method of enabling a multi-boot configuration of a device having programmable logic is disclosed. The method comprises powering up the device using a first configuration bitstream from a first type of configuration device in response to a first command; receiving a reboot command; and reconfiguring the device using a second configuration bitstream from a second type of configuration device in response to a second command which is different than the first command. Circuits enabling a multi-boot configuration of a device having programmable logic are also disclosed.

Abstract: A system for providing a pre-programmed integrated circuit including programmable logic, and method for providing same. The system includes: nonvolatile memory capable of having first data stored therein and an integrated circuit coupled with the nonvolatile memory. The first data is associated with a predetermined design, and the integrated circuit includes programmable logic having a user region and a reserved region. The integrated circuit is configured to obtain the first data from the nonvolatile memory for instantiation of the predetermined design in the reserved region.

Abstract: A hard macro-to-user logic interface of an integrated circuit is described. The integrated circuit includes a core as an application specific circuit block with a transaction interface of a first bit width and includes programmable logic capable of being programmed to instantiate user logic. The user logic has a user interface of a second bit width substantially less than the first bit width. A wrapper circuit couples the user interface and the transaction interface for coupling the core to the user logic.

Abstract: A method of integrating a High-level Language (HLL) function with a Hardware Description Language (HDL) representation of a circuit design can include identifying an attribute of the HDL representation of the circuit design that is resolved at compile time and determining a value for the attribute using an HLL function when compiling the HDL representation of the circuit design.