Abstract: Various approaches for generating an implementation of an electronic circuit design are disclosed. In one approach, one or more configuration bits that have don't care conditions are identified for a LUT block of a design. A dynamic power state for a subset of a first level of logic devices in the LUT block is determined as a function of each identified configuration bit that has a don't care condition. A dynamic power state for a subset of a second level of logic devices is determined as a function of the determined power state for the first level of logic devices. A respective value for each identified configuration bit of the LUT is selected in response to the determined dynamic power states. The respective value is placed into the design for each identified configuration bit.

Abstract: Testing of routing resources in a path between network nodes is provided using simpler nodes to replace more complex IP modules which could be programmed into an FPGA after the routing resources are tested. Further, when it is impractical to generate a pattern from a source node S for testing a network path N to a load, subnetworks are created to perform testing. To provide the subnetworks, a source S? is first provided close to node S that generates signal patterns to route through a path N? to load L. When it is impractical to test a network path N from source to load L, a load L? is further provided close to load L that receives the signal patterns from a routing path N? provided from source S. The paths N? and N? overlap to cover all the routing resources of the path N.

Abstract: A method and apparatus to allow dynamic port provisioning of communication ports within a Programmable Logic Device (PLD). The dynamic port provisioning combines configuration of serial Input/Output (I/O) devices with simultaneous reconfiguration of a portion of programmable logic resources within the PLD and processor functions to implement a particular communication protocol. The dynamic port provisioning is facilitated for a single channel, without affecting the dynamic port provisioning of other communication channels operating within the PLD.

Abstract: Simulation of noise and, more particularly, a coefficient generator for channel modeling, is described. A spectrum memory is for storing sets of constants for respective harmonics. At least one phase noise source is configured for generating phase noise. An Inverse Fourier Transform block is coupled to the spectrum memory and to the at least one phase noise source. The Inverse Fourier Transform block is configured to provide a read address to the spectrum memory for accessing at least one constant of a set of constants of the sets of constants from the spectrum memory and coupled to receive the phase noise from the at least one phase noise source.

Abstract: An integrated circuit with an efuse having an efuse link includes a damage detection structure disposed in relation to the efuse so as to detect damage in the IC resulting from programming the efuse. Damage sensing circuitry is optionally included on the IC. Embodiments are used in evaluation wafers to determine proper efuse fabrication and programming parameters, and in production ICs to identify efuse programming damage that might create a latent defect.

Abstract: An apparatus and method to accurately simulate negative bias and temperature instability (NBTI) and its effect. According to a first simulation method, a simulation netlist is automatically scanned for any P-type devices that are in a conductive state after application of an initial condition. Each conductive P-type device is automatically replaced with an NBTI device model and a first simulation cycle is executed. After the first cycle, each conductive P-type device is again replaced with an NBTI model and a second simulation cycle is executed. In a second simulation method, only those P-type devices transitioning from a non-conductive state to a conductive state are automatically replaced with an NBTI model prior to each half cycle of the second simulation method. The first simulation method provides robustness, while the second simulation method provides worst case verification in less time as compared to the first simulation method.

Abstract: Method and apparatus for a dynamically reconfigurable system monitor (20) are described. A system monitor (20) has registers (206) accessible via a reconfiguration port (201). At least one of the registers may be dynamically reconfigured via the reconfiguration port (201) to select a channel to be monitored or to store an alarm value to be used in monitoring by the system monitor (20). Additionally, the system monitor (20) may be embedded in a columnar block architecture.

Abstract: A communication system includes a transmitter, a communication channel, and a receiver. The transmitter includes a pre-emphasis module, a summing module, a line driver, and a decision feedback pre-emphasis (DFP) module to produce a pre-emphasized serial stream of data based on a communications channel response and an inter-symbol interference level. The receiver includes a linear equalizer, a summing module, a decision module, and a decision feedback equalization (DFE) module. The linear equalizer produces an equalized serial stream of data. The summing module sums at least one data element of the equalized serial stream of data with DFE data elements to produce equalized data elements. The decision module interprets the equalized data elements to produce interpreted data elements to DFE module, which produces the DFE data elements from the interpreted data elements.

Abstract: Method, apparatus, and computer readable medium for modular circuit design for a programmable logic device (PLD) is described. In one example, a circuit design is captured. The circuit design includes a plurality of modules and one or more logic interface macros positioned on a floorplan. Each of the plurality of modules is one of a static module or a reconfigurable module. The one or more logic interface macros include programmable logic of the PLD and are positioned at one or more boundaries between one or more pairs of the plurality of modules. Each of the plurality of modules is implemented using information generated from the capturing step. The modules are assembled using the information generated from the capturing step and implementing step. Routing for a static module can cross a defined implementation area for a reconfigurable module, and a static module can be placed anywhere outside of reconfigurable module areas.

Abstract: A protective mechanism for a probe card cover to prevent the probe card cover or attachment screws extending from the probe card cover from striking a wafer in a test system if the probe card is installed without removing the cover. The protective mechanism includes an elongate member that can be permanently attached to the probe card cover, or attached by screws to the probe card cover. The protective mechanism can be a bar that extends longer than an opening in a probe card holder tray through which probes of the probe card pass during testing. The bar can be hard, yet flexible enough to prevent damage to the probe card holder tray or probe card.

Abstract: A computer-implemented method of placing input/output (I/O) pins of a circuit design for an integrated circuit (IC) can include selecting a bus from a plurality of buses, where the selected bus includes a plurality of I/O pins and is part of an interface, and, for each of a plurality of banks of the IC, determining a cost of assigning the selected bus to the bank according, at least in part, to a measure of proximity of the bank to another bank including a bus of the interface. The method can include selecting an available bank having a lowest cost, assigning at least one of the plurality of I/O pins of the selected bus not assigned to a bank of the IC to the selected bank, and outputting a circuit design including an association of I/O pin(s) of the selected bus to the selected bank.

Abstract: Measuring transit time across an asynchronous first-in-first-out (FIFO) memory can include sampling an indication of a value of a read pointer of the FIFO memory at a sampling frequency that exceeds a frequency of a read clock and a write clock of the FIFO memory. An indication of a value of a write pointer of the FIFO memory can be sampled at the sampling frequency. For each sampling period, a measure of occupancy of the FIFO memory can be calculated according to a sampled pair including the indication of the value of the read pointer and the indication of the value of the write pointer. The measure of occupancy can be averaged over a predetermined number of cycles of the sampling frequency. The averaged measure of occupancy can be output as an indication of transit time across the FIFO memory.

Abstract: A circuit detects symbols transmitted from multiple transmitting antennas to multiple receiving antennas. A distance block for an initial transmitting antenna in an ordering of the transmitting antennas determines a distance value for each symbol in a constellation. A selector block selects a limited number of candidates for the initial transmitting antenna from the symbols having smaller distance values. For each first and successive second transmitting antenna in the ordering, a distance-selector block selects a candidate for the second transmitting antenna for each candidate for the first transmitting antenna. The candidate for the second transmitting antenna is a pairing having a smaller distance value among the pairings of the candidate for the first transmitting antenna and the symbols. An identifier block selects a last candidate having a smaller distance value among the candidates for a last transmitting antenna in the ordering. The last candidate includes the detected symbols.

Abstract: A computer-implemented method of converting a circuit design for a programmable logic device (PLD) to a standard cell circuit design can include unmapping a PLD circuit design to a gate level netlist (110), mapping logic gates of the netlist to functionally equivalent standard cells (120), and including the standard cells within the standard cell circuit design (125). Design constraints for the standard cell circuit design can be automatically generated (135, 140). The design constraints for the standard cell circuit design can be output (145).

Abstract: Methods of detecting unwanted logic in an integrated circuit (IC) design. Any unwanted logic added to a design (e.g., to monitor or interfere with operation of the design) will draw power from one or more power supplies on the IC. Hence, by monitoring power drawn from various portions of a circuit design implemented in an IC, the unwanted logic can be detected and reported to the user. One way of monitoring power draw is by the use of oscillator circuits. If power goes down locally (e.g., due to the operation of unwanted logic), the frequency of an oscillator circuit in that vicinity will be reduced relative to the frequencies of other oscillator circuits in the design, and/or relative to an expected value. When a variation in the relative power consumption is detected, unwanted logic can be inferred and an error signal is output.

Abstract: A method of managing an incremental implementation flow (incremental flow) for a circuit design can include storing dependency management data for the incremental flow for the circuit design and, from a first application, invoking at least one plug-in software component configured to access the dependency management data for the circuit design. The method further can include identifying partitions of the circuit design that must be run during the incremental flow using the plug-in software component.

Abstract: A configuration management system is disclosed. For example, an embodiment of the present invention provides a configuration management system comprising at least one configuration storage device containing configuration data, and a plurality of integrated circuits, coupled to said at least one configuration storage device, where the plurality of integrated circuits are coupled in a loop, where each of the plurality of integrated circuits comprising at least one configuration management controller for managing a configuration of another integrated circuit in the loop in accordance with the configuration data, where the plurality of integrated circuits is deployed in at least one radiation tolerant device.

Abstract: Methods of generating a PLD design implementation according to a design architecture tailored to specified requirements. A hardware description language (HDL) description for the PLD design includes at least one parameter value for the PLD design that will affect the preferred implementation of the design. This parameter value is passed to a high-level language (HLL) function, which is used to determine a tailored design architecture in accordance with the specified needs of the target application. The HLL function returns data specifying the tailored design architecture. This data is used in generating an implementation of the PLD design that follows the constraints imposed by the tailored design architecture. The result can be, for example, a logic gate representation of the PLD design, a netlist of the design, or a bitstream implementing the design in a target PLD.

Abstract: Method and apparatus for indicating to a coprocessor when the coprocessor can update internal register content thereof without negative repercussion to a processor is described. A controller is coupled between the coprocessor and a processor, where the controller is configured with a state machine to track the instruction through pipeline stages of the processor.

Abstract: A network processor, disposed on an integrated circuit can include an ingress unit having a dual port block random access memory and an egress unit having a dual port block random access memory. The network processor further can include a network interface configured to write packetized data to the ingress unit and read packetized data from the egress unit as well as a coordination processor configured to coordinate movement of data between the network interface, the ingress unit, and the egress unit.