Abstract: Circuit and methods for testing a memory device are disclosed. According to one aspect of the invention, a circuit for testing an asynchronous data transfer comprises a first circuit receiving a stream of data in response to a clock signal in a first clock domain. A second circuit coupled to the first circuit receives the stream of data from the first circuit in response to a low level of an empty signal in the second clock domain. A comparator circuit coupled to receives the stream of data and the output of the second circuit. Specific applications to dual port RAMs as well as implementations in a programmable logic devices are disclosed. Various methods of testing an asynchronous data transfer are also disclosed.

Abstract: Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, specification data is received that includes attributes of the memory system. A logical description of the memory system is generated in response to the specification data. The logical description defines a memory component and a memory-interconnection component. A physical description of the memory system is generated in response to the logical description. The physical description includes memory circuitry associated with the integrated circuit defined by the memory component. The memory circuitry includes an interconnection topology defined by the memory interconnection component.

Abstract: Method for power estimation for mobile devices for content downloading is described. More particularly, likelihood of download success is determined responsive to user selection of downloadable content after establishment of a connection between a mobile device and a network. Capabilities of the mobile device are obtained. The power level of the mobile device is obtained. At least one download data rate is determined. A likelihood of success for downloading the downloadable content selected responsive to the at least one download data rate, the power level of the mobile device, and at least one capability from the capabilities of the mobile device is determined.

Abstract: Generation of a circuit design using a command language. The various approaches include generating in a memory arrangement respective instances of design blocks in response to user-entered commands that specify creation of the instances. Matrix-relative positions of the instances of design blocks are established in the memory arrangement in response to at least one user-entered command that specifies respective matrix positions of the instances. Representative connections between the instances are generated in the memory arrangement in response to a user-entered command having no specification of the connections.

Abstract: A capacitive interposer (caposer) is disposed inside an integrated circuit package between a die and an inside surface of the package. Conductive layers within the caposer constitute a bypass capacitor. In a through-hole caposer, micro-bumps on the die pass through through-holes in the caposer and contact corresponding landing pads on the package. As they pass through the caposer, power and ground micro-bumps make contact with the plates of the bypass capacitor. In a via caposer, power and ground micro-bumps on the die are coupled to power and ground landing pads on the package as well as to the plates of the bypass capacitor by power and ground vias that extend through the caposer. In signal redistribution caposer, conductors within the caposer redistribute signals between die micro-bumps and package landing pads. In an impedance matching caposer, termination structures within the caposer provide impedance matching to a printed circuit board trace.

Abstract: A memory cell with a logic bit has a first one-time-programmable (“OTP”) memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP memory element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element.

Abstract: In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.

Abstract: A method and apparatus for a clock and data recovery circuit that includes a set of serializer/deserializer (SERDES) circuits that are adapted to sample progressively delayed versions of an input data stream. The sampling rate is slightly higher than the data rate of the input data stream, which produces duplicate bits in the detected data stream. Error and offset matrices are used to generate an index pointer into a detected data matrix to extract the correct data bits from the duplicate bits of the detected data matrix. Down-sampling of the corrected data is performed to populate a ring buffer. Data is then extracted from the ring buffer using a clock signal whose frequency is adapted from the sampling clock signal used by the SERDES to prevent underflow/overflow of the ring buffer.

Abstract: A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming “cells” or “packets” stored in the memory in the switch based on the time of storage in the BRAM. A non-blocking memory architecture is implemented that allows for a scalable N×N memory structure to be created (N=number of input and output ports). A write controller stripes the data across this N×N memory to prevent data collisions on read in or read out of data. The data is scheduled for read out of this N×N shared memory buffer based on priorities or classes in the class queues, with priorities being set by a user, and then data is read out from the BRAM.

Abstract: A method and apparatus to facilitate low-power consumption through a configurable suspend mode of operation of a PLD, the PLD comprising an application logic block coupled to receive configuration data bits and adapted to implement a logic application in response to the configuration data bits, a suspend pin coupled to receive a suspend signal, a write protect block coupled to the application logic block and adapted to prohibit the application logic block from changing logic states in response to a suspend mode initiated by the suspend signal; and an awake pin adapted to provide an awake signal that is indicative of a status of the suspend mode.

Abstract: Preventing transistor damage to an integrated circuit is described. The circuit includes a switch with a first pair of p-type transistors respectively coupled in source-drain parallel with second pair of p-type transistors for preventing Negative Bias Temperature Instability (“NBTI”) damage to the second pair of p-type transistors. The switch is configured to such that when in a state associated with causing, or potentially causing, NBTI damage, both of the second pair of p-type transistors are in an OFF state for preventing NBTI damage thereto.

Abstract: An automatic calibration scheme is provided, which calibrates the equivalent taps per period ETT/P every time a delay lock loop is used. More specifically, a digital phase shifter is used to measure equivalent taps per period ETT/P. Alternately, the digital phase shifter is used to directly measure the signal delay through a clock phase shifter of the delay lock loop, thereby directly determining the high frequency and low frequency overhead constants.

Abstract: A method of operating a programmable logic device, including the steps of enabling resources of the programmable logic device being used in a circuit design implemented by the programmable logic device, and disabling unused or inactive resources of the programmable logic device that are not being used in the circuit design. The step of disabling can include de-coupling the unused or inactive resources from one or more power supply terminals. Alternatively, the step of disabling can include regulating a supply voltage applied to the unused or inactive resources. The step of disabling can be performed in response to configuration data bits stored by the programmable logic device and/or in response to user controlled signals. The step of disabling can be initiated during design time and/or run time of the programmable logic device.

Abstract: A model and method are provided for lowering device jitter by controlling the stackup of PCB planes so as to minimize inductance between a FPGA and PCB voltage planes for critical core voltages within the FPGA. Furthermore, a model and method are provided for lowering jitter by controlling the stackup of package substrate planes so as to minimize inductance between a die and substrate voltage planes for critical core voltages within the die.

Abstract: Various embodiments of the present invention relate to circuits for and methods of generating a bias current for a plurality of data transceivers on an integrated circuit. According to one embodiment, an integrated circuit having a plurality of data transceivers comprises a first data transceiver receiving a reference voltage. A plurality of data transceivers are preferably coupled to the first data transceiver, where each the data transceiver of the plurality of data transceivers receives a reference current based upon the reference voltage from the first data transceiver. According to alternate embodiment of the invention, an external resistor is coupled to a data transceiver to generate a fixed bias current in addition to a variable bias current. A method of generating a bias current for a plurality of data transceivers is also disclosed.

Abstract: An FPGA is laid out as a plurality of repeatable tiles, wherein the tiles are disposed in columns that extend from one side of the die to another side of the die, and wherein each column includes tiles primarily of one type. Because substantially all die area of a column is due to tiles of a single type, the width of the tiles of each column can be optimized and is largely independent of the size of the other types of tiles on the die. The confines of each type of tile can therefore be set to match the size of the circuitry of the tile. Rather than providing a ring of input/output blocks (IOBs) around the die periphery, IOB tiles are disposed in columns only. Where more than two columns worth of IOBs is required, more than two columns of IOB tiles can be provided.

Abstract: Method and apparatus for coding and, more particularly, for Reed-Solomon encoding and decoding with puncturing are described. At least one core is generated responsive to a puncture pattern input provided to a core generator. The core may be an encoder core or a decoder core, or a combination thereof such as a CODEC. For this generation, the puncture pattern input, including puncture patterns, are for a polynomial generator. The at least one core is configured to provide encoding or decoding, as applicable, responsive to the puncture patterns for which it was configured as generated with the core generator.

Abstract: Reset of an interface device of an integrated circuit is described. A Peripheral Component Interconnect Express core is instantiated as an application specific circuit block in the integrated circuit. The core has a reset block configured to be in either a hierarchical reset mode or a hierarchical/separate reset mode. In the hierarchical reset mode, the reset block is configured to assert a reset signal selected of a plurality of reset signals and to automatically assert each and every other reset signal of the plurality of reset signals lower in a reset hierarchy than the reset signal selected.

Abstract: A method of validating a bitstream loaded into a circuit having a programmable circuit is disclosed. According to one embodiment, the method comprises steps of loading a configuration bitstream comprising an error detection command at an input of the circuit; decoding the bitstream; providing a signal indicating that an error detection should be performed to a state machine when an error detection command has been decoded; and restarting the loading of the configuration bitstream if the signal has not been received. A device having a programmable circuit is also disclosed.

Abstract: A method and apparatus for substantially eliminating noise induced errors caused by a premature start-up sequence between configuration of an integrated circuit (IC) and execution of functional test vectors. A noise elimination sequence is executed, whereby the configuration bitstream associated with the IC is scanned for the existence of a start-up sequence. If found, the start-up sequence is stripped from the configuration bitstream and the IC is then configured using the modified configuration bitstream. The input/output (I/O) pins of the IC remain in a deactivated state until a startup sequence is transmitted to the IC via a Joint Test Action Group (JTAG) port of the IC, which then allows IC testing to commence.