Abstract: A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.

Abstract: Described are various methods and systems for encrypting/decrypting configuration data for programmable logic devices. In configuration data defining a number of separately encrypted subdesigns, or “cores,” each subdesign includes a shared password or a unique authentication code to ensure the designs belong together. Other embodiments prohibit the overwriting of configuration memory to prevent the inclusion of unauthorized designs. Still other embodiments protect key secrecy while enabling users to read, write, and verify the keys.

Abstract: Method and apparatus are described for determining when a convolution decoder is out of synchronization. Normalizations from a convolutional decoder are counted to provide a normalization count, and errors from the convolutional decoder are counted to provide an error count. One of the normalization count and the error count is compared to a first threshold associated with the selected one of the normalization count and the error count. The other of the normalization count and the error count is compared to a second threshold in response to meeting the first threshold, such as bit errors per X normalizations or normalizations per Y bit errors. From this latter comparison, an indicator is generated as to whether the convolutional decoder is synchronized or not.

Abstract: An integrated circuit having an embedded first-in, first-out (“FIFO”) memory system uses an embedded block random access memory (“BRAM”). Counters operate in both the read and write clock domains. A binary adder adds a first selected offset value and to a first pointer address, and the sum is converted to a first gray code value. The first gray code value is compared to a second gray code value that represents a second pointer address. If the first gray code value equals the second gray code value, the output of the comparator is provided to a logic block that produces a status flag (e.g. ALMOST FULL or ALMOST EMPTY) in the correct clock domain.

Abstract: A method and apparatus for providing non 2:1 current in a Gilbert cell mixer is disclosed. The Gilbert cell mixer provides lower voltage operation, lower LO drive and better linearity. Additional current sources are provided to drive the lower, source-coupled transistor pair thereby allowing operation of the switch transistors with lower current.

Abstract: A power-on reset circuit for generating a reset signal for an associated IC device includes a pull-up resistor connected between a supply voltage and a tracking node, a pull-down transistor connected between the tracking node and ground potential, and a voltage divider circuit connected between the supply voltage and ground potential. The voltage divider circuit has a first ratioed voltage node coupled to the gate of the pull-down transistor. For some embodiments, the voltage divider circuit includes a first resistor connected between the voltage supply and the first ratioed voltage node, a second resistor connected between the first ratioed voltage node and a second ratioed voltage node, a third resistor connected between the second ratioed voltage node and ground potential, and a shunt transistor connected between the second ratioed voltage node and ground potential has a gate responsive to the reset signal.

Abstract: A delay line for a digital clock manager includes a tap delay structure and a trim delay structure. The trim delay structure includes a first buffer coupled to receive a clock signal from the tap delay structure, and in response, provide a delayed clock signal to a set of clock lines. The trim delay structure also includes a capacitive trim unit having a plurality of capacitive trim elements tapped off the set of clock lines. The capacitive trim elements are selectively enabled or disabled, thereby introducing additional delay to the delayed clock signal on the set of clock lines. Each capacitive trim element can include a transmission gate structure, which is turned on to introduce significant junction capacitance to the set of clock lines. The trim delay structure can also include a second buffer adapted to buffer the delayed clock signal on the set of clock lines.

Abstract: The circuits and methods of the present invention relate to circuits for generating a multiplied clock signal based upon a reference clock signal, and circuits using the clock signal to deserialize data. According to one embodiment of the invention, a circuit comprising a counter is coupled to generate a count representative of the period of the input clock signal. A divider circuit coupled to the counter generates a divided count. Finally, a clock generator coupled to the divider circuit outputs an output clock signal having a period which is based upon the divided count. According to other embodiments, circuits and methods disclose receiving serial data using the output clock signal, and outputting the data as parallel data using the reference clock.

Abstract: A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.

Abstract: A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.

Abstract: A method for detecting a pattern from an arithmetic logic unit (ALU) in an integrated circuit. The method includes the steps of: generating an output from an ALU; bitwise comparing the ALU output to a pattern to produce a first output; inverting the pattern and comparing the ALU output with the inverted pattern to produce a second output; bitwise masking the first and second outputs using a mask of a plurality of masks to produce third and fourth output bits; combining the third and fourth output bits to produce first and a second output comparison bits; and storing the first and second output comparison bits in a memory.

Abstract: An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders, where the plurality of adders are controlled by some bits of the second opcode, and where a first adder of the plurality of adders adds a plurality of input bits to produce first summation bits and a first carry bit; the first adder operating concurrently with the other adders of the plurality of adders.

Abstract: A method of relieving timing-based congestion during physical implementation of a programmable logic device can include routing a placed circuit design for the programmable logic device in a delay mode and calculating an initial delay for connections of the circuit design based upon the routing step. A final delay for connections of the circuit design can be predicted with connection sharing removed. Connections of the circuit design that do not conform with timing constraints based upon at least one of the initial delays or the final delays can be identified. Accordingly, a detailed routing of the circuit design or further optimization of the circuit design can be selectively performed according to the determination regarding the timing constraints.

Abstract: Method and apparatus for assessing coverage of production rules of a programming language by one or more test programs. A set of production rules that define the programming language is input, along with a test program. The production rules that are covered by the test program are determined and coverage of production rules by the test program is reported.

Abstract: An integrated circuit (“IC”) includes a phase-locked loop (“PLL”) with a controllable oscillator embedded in the integrated circuit. A phase-lock circuit provides a lock control signal to the controllable oscillator; and a digital-to-analog converter (“DAC”) provides an oscillator adjustment signal to the controllable oscillator according to a digital code. The digital code is generated by an adjustment circuit configured in the fabric of a programmable logic device, or embedded in the IC, for example. In a particular embodiment, the DAC adjusts the PLL to reduce differential mode voltage in the phase-lock circuit.

Abstract: Method and apparatus for a dynamically reconfigurable, including partially reconfigurable, multi-stage crossbar switch using configurable circuitry is described. Configurable circuitry is configured to provide the multi-stage crossbar switch with at least: a first stage configured from a first portion of the configurable circuitry to provide a first plurality of crossbars; a second stage configured from a second portion of the configurable circuitry to provide a second plurality of crossbars; and a third stage configured from a third portion of the configurable circuitry to provide a third plurality of crossbars. The first stage having inputs, and the third stage having outputs. The inputs and the outputs user selectable for responsive path configurable input-to-output cross-connectivity via the first stage, the second stage and the third stage using the first interconnects and the second interconnects.

Abstract: A method of routing a design on a programmable logic device (PLD) includes generating a database that identifies the correspondence between routing resources of the PLD and programming frames of the PLD. A first set of programming frames required to implement the logic of the design is identified, and the cost associated with using the first set of programming frames is eliminated. A second set of programming frames that are not used to implement the logic of the design is also identified, and the cost associated with using the second set of programming frames is maximized. Interconnect networks of the design are then routed, taking into account the costing of the programming frames. When a programming frame from the second set is used, the cost associated with using this programming frame is eliminated. This method minimizes used programming frames and maximizes unused programming frames, thus reducing PLD configuration time.

Abstract: A method (200) of placing inputs, outputs, and clocks in a circuit design can include assigning (205) initial locations to inputs and outputs of the circuit design, selecting (210) at least one component type for the circuit design, and generating (215) a cost function having parameters corresponding to the selected component type. The method further can include annealing (220) the selected component type using the cost function and determining design constraints (225) for the selected component type according to the annealing step. The method can repeat to process additional component types such that design constraints determined for each additional component type do not violate design constraints determined for prior component types.

Abstract: A method of designing a programmable logic device can include receiving a modification to a programmable logic device that has been floorplanned. Modules of the programmable logic device that have been changed by the modification can be identified. The changed modules can be floorplanned thereby determining a placement solution that does not violate boundaries of unchanged modules. The programmable logic device then can be placed and routed.

Abstract: An integrated circuit, such as a programmable logic device, implements a single bit transition counter in logic. The counter preferably comprises a first stage receiving a clock signal having a first clock rate and generating a least significant bit in a count. A plurality of intermediate stages are coupled to the first stage, where each intermediate stage receives an output from the immediate previous stage and an inverted output of each other previous intermediate stage, and generates a next most significant bit in a count. Finally, a last stage of the counter receives an inverted output of each previous intermediate stage except the immediate intermediate previous stage and generating a most significant bit in a count.